Interbus buffer for use between a pseudo little endian bus and a

Details Interbus buffer for use between a pseudo little endian bus and a Interbus buffer for use between a pseudo little endian bus and a

1994-08-02

1997-05-06

Treat, William M.

395380, G06F 1300

Patent

active

056279752

ABSTRACT:
An interbus buffer (18) coordinates data transfers between two different sized buses. The first bus (processor bus) allows data to be ordered according to either a big endian protocol or a "munged" little endian mode. The second bus (local bus) allows data to be ordered according to either a big endian protocol or a true little endian mode but does not define a transaction size. The disclosed interbus buffer coordinates interbus data transfers in spite of the variety of different transaction sizes and operating modes.

REFERENCES:
patent: 5132898 (1992-07-01), Sakamura et al.
patent: 5191581 (1993-03-01), Woodbury et al.
patent: 5313231 (1994-05-01), Yin et al.
patent: 5388227 (1995-02-01), McFarland
patent: 5423010 (1995-06-01), Mizukami
patent: 5446482 (1995-08-01), Van Aken et al.
patent: 5446651 (1995-08-01), Moyse et al.
patent: 5446847 (1995-08-01), Keeley et al.
James, "Multiplexed Buses: The Endian Wars Continue", 1990.

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