Electricity: electrical systems and devices – Miscellaneous
Patent
1987-02-19
1988-11-08
Kucia, R. R.
Electricity: electrical systems and devices
Miscellaneous
174 685, 361412, 439 44, 439 74, H05K 111
Patent
active
047837225
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an interboard connection terminal for connecting boards, such as a large chip and a wiring board, and a method of manufacturing the same.
BACKGROUND ART
For example, a solder bump connecting method (flip chip bonding method) as described in Japanese Patent Application Nos. 43-1654 and 43-28735 is known as a method to connect terminals of a chip and a wiring board. According to this connecting method, as shown in FIG. 1, a plurality of electrodes b formed on chip a and electrode portions d on wiring board c for supporting the same are directly bonded through solder bumps e. Since the thermal expansion coefficients of chip a and wiring board c are different from each other, a shear strain occurs in solder bumps e when the temperature changes. This shear strain increases as the distance between solder bumps e and chip center f increases. Therefore, the larger the chip size g, the fewer thermal cycles occur before a bump breaks, as shown in FIG. 2. As a result, a region capable of arranging solder bumps therein is limited, depending on an allowable shear strain. For example, when a silicon chip is to be connected to a ceramic wiring board, the best possible solder bump arrangement region is about 2.5 mm in radius from the chip center, as shown in Japanese Patent Disclosure Nos. 50-137484 and 59-996. Thus, with a conventional solder bump connecting method, since the best possible solder bump arrangement region is limited in the vicinity of the chip center, it is difficult to increase the number of terminals. Since a distance between an element located outside the best possible solder bump arrangement region in a chip and a solder bump is increased, wiring for connecting them is elongated, resulting in time required for arranging the wire. Furthermore, as shown in FIGS. 3(A) and 3(B), as the chip size is increased, gap deviation j between a chip and wiring board, depending on the warp and undulation of the chip or wiring board, is increased (gap deviation j=j2-j1 where j1 is a gap at a central portion and j2 is a gap at an end portion of the chip). It is difficult to absorb such gap deviation j by only a single stage of solder bumps e. In the worst case, since a vertical compressive force acts to squeeze adjacent solder bumps in the horizontal direction, as shown in FIG. 4, some terminals may be short-circuited. When the gap deviation becomes too large, a bump may be separated from either one of the boards, thus electrically disconnecting the boards.
With conventional unstacked stage solder bump connection, since the gap deviation and hence a mechanical stress cannot be sufficiently absorbed, the rear surface of a chip cannot be completely fixed to a heat sink. Therefore, cooling must be taken to prevent this, resulting in a complex cooling structure.
As a method for eliminating such drawbacks of the conventional solder bump connecting method, a method is proposed in Japanese Patent Disclosure No. 59-996. In this method, solder terminals of a chip and a wiring board are connected through through-holes formed in an intermediate board. More specifically, according to this method, as shown in FIG. 5, through-holes i are formed in intermediate board h having a thermal expansion coefficient of an intermediate value between those of chip a and wiring board e, and solder, or Ag or Cu which has solderability is charged in through hole i (charged only inside board h, as shown in FIG. 5, or charged into board h to partially project from the two surfaces of board h, as indicated by i in FIG. 6(A)), in order to decrease the shear strain caused in solder bumps e covering chip electrodes b and in solder bumps e' covering wiring board electrodes d. Electrodes b of chip a and electrodes d of wiring board c are connected to each other through solders e and e'. In this method, as shown in FIG. 6(A), intermediate board h is inserted between chip a and wiring board c, and solders e and e' are melted and connected to each other. However, since the solder is thermally melted, upper
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Egawa Yutaka
Matsui Norio
Osaki Takaaki
Sasaki Shin-ichi
Kucia R. R.
Nippon Telegraph and Telephone Corporation
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