Inter-silicide capacitor

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

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Details

257296, H01G 406, H01L 2978

Patent

active

052185117

ABSTRACT:
A method produces a capacitor. On a substrate, a polysilicon layer is formed over an insulating region. A first metal-silicide layer is formed on top of the polysilicon layer. A dielectric layer is formed on top of the first metal-silicide layer. A second metal-silicide layer is formed on top of the dielectric layer. The second metal-silicide layer and the dielectric layer are etched to form a top electrode and dielectric region. The first metal-silicide layer and the polysilicon layer are etched to form a bottom electrode.

REFERENCES:
patent: 4922312 (1990-05-01), Coleman et al.
patent: 4975753 (1990-12-01), Ema
patent: 5017982 (1991-05-01), Kobayashi
patent: 5132756 (1992-07-01), Matsuda
C. Kaya, H. Tigelaar, J. Paterson, M. de Wit, J. Fattaruso, D. Hester, S. Kiriakai, K. Tan, F. Tsay, "Polycide/Metal Capacitors for High Precision A/D Converters", IEDM, 1988, pp. 782-785.
T. Ono, T. Mori, T. Ajioka, T. Takayashiki, "Studies of Thin Poly Si Oxides for E and E.sup.2 PROM", IEDM, 1985, pp. 380-383.
T. Iida, M. Nakahara, S. Gotoh and H. Akiba, "Precise Capacitor Structure Suitable for Submicron Mixed Analog/Digital ASICs", Custom Integrated Circuits Conference, 1990, pp. 18.5.1-18.5.4.
Jim Paterson, "Adding Analog, EPROM and EEPROM modules to CMOS Logic Technology: How Modular?", IEDM, 1989, pp. 16.1.1-16.1.3.

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