Multiplex communications – Wide area network – Packet switching
Patent
1986-12-22
1990-04-03
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
3408255, H04J 302
Patent
active
049146530
ABSTRACT:
Processors (101) of a multiprocessor system (FIG. 1) communicate across bus (150) via a low-latency packet protocol featuring per-logical channel input queues (143) and output queues (144), different per-processor priorities for sending data packets (FIG. 10) and data packet-acknowledging "quick" messages (FIG. 11), and separate buffers (923; 918) for receiving data packets and "quick" messages, respectively. Transmitted data packets afflicted by error, receive buffer overflow, and input queue-full conditions are discarded by the receiving processor and are retransmitted by the sending processor.
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Bishop Thomas P.
Davis Mark H.
Horn David N.
Surratt Grover T.
Welsch Lawrence A.
American Telephone and Telegraph Company
Jung Min
Olms Douglas W.
Volejnicek David
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