Inter-metal-dielectric planarization process

Details Inter-metal-dielectric planarization process Inter-metal-dielectric planarization process

1992-10-08

1995-02-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437235, 437238, H01L 2144

Patent

active

053937082

ABSTRACT:
A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via combining TEOS with ozone silicon oxide pyrolytic deposition with plasma-enhanced deposition processes and spin-on-glass processes. A first insulator layer is provided over the conductive layer by plasma-enhanced chemical vapor deposition (PECVD). This insulator layer is covered with a layer of TEOS with ozone deposited silicon oxide by pyrolytic chemical vapor deposition (THCVD). The TEOS with ozone silicon oxide layer will fill the irregular trenches and holes in the conductive layer structure not filled by the first insulator layer. The TEOS with ozone layer is anisotropically etched back leaving the TEOS with ozone layer only in the trenches and holes of the layer structure. A second insulating layer is deposited by PECVD and then is covered by at least one spin-on-glass layer to fill the wider valleys of the irregular structure. The spin-on-glass layer is cured, then partially blanket anisotropically etched through its thickness to the underlying second oxide layer at its highest points and leaving the spin-on-glass layer portions in the valleys. A top dielectric layer is deposited over the spin-on-glass layer to complete the planarization.

REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.
patent: 4885262 (1989-12-01), Ting et al.
patent: 5266525 (1993-11-01), Morozumi
Kawai, M., et al. "Interlayered Dielectric Planarization with TEOS-CVE and SOG", Proc. IV Intern'tl IEEE VLSI Conf. (1988) pp. 419-425.
Lee, J. G., et al. "SACVD: A New Approach for 16 Mb Dielectrics," Semicond. International, May 1992, pp. 116-120.

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