Inter-metal dielectric layer

Details Inter-metal dielectric layer Inter-metal dielectric layer

2000-11-14

2002-06-18

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000

Reexamination Certificate

active

06407454

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a method for manufacturing intermetal dielectric (IMD) layers by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. High Density Plasma—Chemical Vapor Deposition (HDP-CVD) is mainly applied to dense thin films formed under low temperatures, wherein, the basic material, silicon, is placed in the plasma in vapor state to form the thin films. Such thin films are all better than those formed by “Plasma Enhanced Chemical Vapor Deposition (PECVD)” no matter in the Gap-Fill capability or the effect of density; thereby, it is widely used for inter-metal dielectric (IMD) layers between metal parts, dielectric semiconductors between every two of multiple internal connecting layers and in forming special metallic layers of tungsten, aluminum or copper.
2. Description of the Prior Art
The method of High Density Plasma—Chemical Vapor Deposition (HDP-CVD) is established by extending of a series of processes, such as Deposition-Etching-Deposition (Dep-Etch-Dep), the process includes:
a deposition process, from forming of a film to appearing of prongs, in the process, a dielectric layer is deposited in the gaps between parts of metal conductors, when the dielectric layer is deposited on the lateral walls in the gaps between the metal parts before forming a crevice, the deposition process is terminated;
an etching and sputtering process to form a corner plane, in the process, wafers are moved to an etching chamber, by a process of sputtering with argon ions, the prongs formed in the foregoing step are removed to form a corner plane;
another deposition process, wherein, the wafer with the plane formed by removing the prongs is once more processed by deposition to have a dielectric layer in the gaps;
by the repeated Dep-Etch-Dep process, the gaps in the metal parts are fully filled with dielectric.
The number of times in repeating the process depends on the widths of the gaps and the aspect ratio of the pattern on the base plate, the conventional High Density Plasma—Chemical Vapor Deposition (HDP-CVD) chamber has two combined functions, i.e., deposition of oxide and etching of argon ions that can be simultaneously proceeded in the same chamber. The deposition forming prongs and the etching and sputtering process are two different kinds of phenomenon of physics and chemistry. However, the two different kinds of phenomenon can be intercrossingly used in the whole method, To fill the dielectric in the gaps between metal parts, control of the amount of bias voltage of the power of radio frequency in the High Density Plasma—Chemical Vapor Deposition (HDP-CVD) process is required.
In the conventional technique, the full flow in forming a dielectric layer between metal parts, such as is depicted in
FIG. 1A and 1D
, includes:
providing a base
100
which is processed by lithography and etching to form a metallic layer
101
with a pattern and a pluratity of gaps
102
each being disposed between every two metal parts;
forming on the metallic pattern layer
101
a dielectric layer
103
which is formed from fluorine silicate glass by high density plasma deposition and fills the metallic pattern layer
101
and the gap
102
between every two metal parts;
providing a chemical-mechanic polishing to make the dielectric layer
103
plane;
forming a covering oxide layer
105
by plasma enhancing deposition.
Wherein, it needs more time to render the dielectric layer
103
in the gap
102
between every two metal parts and formed from fluorine silicate glass by high density plasma deposition to get the desired thickness, because elevated rate of deposition can make the gap
102
between every two metal parts tunable to be completely filled, and this will influence characteristic of the circuit.
Thereby, another conventional technique provides an embedment process in the dielectric layer forming technique between every two metal parts to solve the aforesaid defects such as are shown in
FIGS. 2A
to
2
E. The embedment process uses a deposition method with faster rate of deposition to form a thicker dielectric layer formed from fluorine silicate glass by high density plasma deposition after filling the gap between every two metal parts, the process includes:
providing a base
200
which is processed by lithography and etching to form a metallic layer with a pattern
201
and a plurality of gaps
202
each being disposed between every two metal parts;
forming on the metallic pattern layer
201
a first dielectric layer
203
which is formed from fluorine silicate glass by high density plasma deposition and fills onto the metallic pattern layer
201
and the gap
202
between every two metal parts;
forming on the first dielectric layer
203
a second dielectric layer
204
which has a kind of oxide deposited as a sacrificial oxide;
providing a chemical-mechanic polishing to make the second dielectric layer
204
plane;
forming a covering oxide layer
205
by plasma enhancing deposition.
Unfortunately, such an embedment process has inevitably the following defects as shown in FIG.
4
:
1. The embedment process has complicated steps.
2. It is subjected to forming slits.
3. The multiple layers of interfaces are subjected to attachment of water vapor.
SUMMARY OF THE INVENTION
In view of the above limitations and inevitable defects resided in the conventional arts, the present invention discloses merging of the two steps in the embedment process (which requires two machines)—“forming on the metallic pattern layer
201
a first dielectric layer
203
” and “forming oil the first dielectric layer
203
a second dielectric layer
204
” —wherein, the two steps arc completed in only one machine. The steps executed on the machine include filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP. In this way, in the whole flow of manufacturing, it is no necessity to increase burden on operators, and using and allocation of machines can be reduced, thereby, the present invention has the advantages of elevating production rate, reducing deposition steps, avoiding creating of slits and reducing generation of interfaces.
The present invention has an object to provide a method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. Wherein, the two steps in the conventional embedment process arc completed in only one machine. The steps include filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using a fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CUT. The process includes:
providing a base which is processed by lithography and etching to form a metallic layer with a pattern and a plurality of gaps each being disposed between every two metal
forming on the metallic pattern layer a first dielectric layer and the gap between every two metal parts, then forming on the first dielectric layer a second dielectric layer; the first dielectric layer is formed from fluorine silicate glass by high density plasma deposition and fills the metallic pattern layer and the gap between every two metal parts; the second dielectric layer is formed on the first dielectric layer by deposition of fluorine silicate glass by high density plasma deposition with low bias voltage;
providing a chemical-mechanic polishing to make the second dielectric layer plane;
forming a covering oxide layer by plasma enhancing deposition.

Affiliated with

Also associated with

Rating

Inter-metal dielectric layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Inter-metal dielectric layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Inter-metal dielectric layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2936021