Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-02-04
2003-07-08
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S700000, C438S701000, C438S702000
Reexamination Certificate
active
06589870
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an inter-layer connection structure, a multi-layer printed circuit board (PCB), and production processes therefor. More particularly, the invention relates to an inter-layer connection structure which allows high density packaging and high density wiring, and to a built-up printed circuit board with the structure.
BACKGROUND OF THE INVENTION
In known methods of the above type, an insulating layer having a thickness of 40 to 80 &mgr;m (micrometers) may be used. Vias (openings) 100 &mgr;m or less in diameter formed in the insulator occasionally fail to meet desired yields due to residue of insulator in the bottom of the vias. Inadequate stability or reliability of inter-layer connection due to insufficient conditioning or cleaning of conductor pads under the vias before plating may also occur, depending on the insulator material or process method.
One conventional method for producing a stud bump interconnection structure as part of a PCB is referred to as a via post method. As shown in FIGS.
6
(
a
) to
6
(
f
), this method comprises the steps of: (a) forming a lower circuit layer
102
on a core circuit board
100
; (b) depositing a thin conductive layer
104
over the lower circuit layer (e.g., by electroless plating), then applying or laminating a plating resist
106
on the conductive layer, and thereafter removing bump forming portions of the plating resist by developing same. Stud bumps
108
are formed in the bump forming portions by electro-plating followed by removing the plating resist, and etching away the thin conductive layer
104
. An insulating resin is applied (FIG.
6
(
e
)) on the resulting board to form an insulating layer thereon and then an upper portion of the insulating layer is polished to provide a planarized surface
110
. An upper circuit layer
112
is then formed on the planarized surface
110
.
In the aforesaid process, the electro-plating is applied only to openings formed in the plating resist and, therefore, it is difficult to form bumps of a uniform height, occasionally resulting in formation of over-deposited or under-deposited bumps. This is because the current density varies depending on the distribution density of the stud bump vias and the position thereof within a work area, i.e., whether located in a central portion or a peripheral portion of the work area. In the polishing step, the over-deposited bumps may protrude due to insufficient polishing, and/or the under-deposited bumps may remain coated with the resin and thus unexposed, both of course undesirable results with respect to PCB manufacture.
For formation of a stud bump structure, the bumps should have a height equal to or greater than the thickness of the polished insulating layer, so that the plating resist should be applied to a corresponding thickness. This makes it difficult to remove small areas of resist by development to form via holes of relatively small diameters. As in the photo via method and the laser via method described above, the pretreatment prior to the plating tends to be insufficient to remove the developed resist from the bottom portion of the smaller diameter via holes, thereby possibly resulting in unreliable inter-layer connections.
When small diameter stud bumps
108
are formed, the stud bumps may have a vase-like shape with a portion
114
thereof being bulged as shown in FIG.
7
. Therefore, air
116
may be trapped when the insulating layer is formed by application of a liquid insulating resin. This in turn may result in insufficient insulation reliability.
Another method referred to as open area processing is known for producing a built-up printed circuit board having a stud bump structure. Japanese Examined Patent Publication No. 7-10030 (1995) discloses a double-layered metal etching method for the build-up printed circuit board of the stud bump structure. As shown in FIGS.
8
(
a
) to
8
(
f
) of Applicants' drawings, this method comprises the steps of: (a) forming two layers
122
,
124
of different metals on a core circuit board
120
, and applying a positive resist
126
thereon; (b) subjecting the positive resist
126
to exposure and development, then etching the upper metal layer
124
; (c) etching the lower metal layer
122
; (d) subjecting the positive resist
126
again to exposure and development; and etching the upper metal layer
124
to form a stud bump
128
. An insulating resin
130
is applied on the resulting board and cured to form an insulating layer. In FIG.
8
(
f
), a surface portion of the insulating layer is polished to a level
132
(hidden in FIG.
8
(
e
)), and an upper circuit layer
134
is then formed thereon.
The aforesaid method, however, requires two kinds of metals
122
and
124
and two etching steps, thereby increasing manufacturing costs. Further, as shown in
FIG. 9
, the stud bump formed from the upper metal layer
124
tends to have a trapezoidal shape and the etching of the lower metal layer
122
by using the upper metal layer
124
as a “mask” tends to further broaden the bottom land width. Therefore, a land
140
of the lower metal pattern layer may contact an adjacent circuit conductor, as shown in
FIG. 9
, to cause a circuit short, which makes fine line etching difficult.
To meet the requirements for high density packaging and fine-pitch chip-mounting on built-up printed circuit boards, it is important to form interconnection patterns with higher density and flexibility, for which various kinds of interconnection methods are proposed. Particularly, via holes for interconnection between conductive layers are required to have a smaller diameter on the order of not greater than 100 &mgr;m. There are known in the art some conventional methods for the interconnection between conductive layers, known as a photo via or laser via method, which are so-called closed-area processing wherein vias are formed in an insulator of 40 to 80 &mgr;m thickness and then plated with copper for inter-layer connection.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide an inter-layer connection structure with a bump via of a small diameter for interconnection between lower and an upper electrical circuits. The bump via can be formed at lower costs with a higher yield by curving a copper foil on a substrate by a controlled etching method (herein referred to as “etch down”), while using a conventional production process and materials for printed circuit boards.
It is another object of the invention to ensure higher interconnection reliability by interconnecting a bump via and an upper circuit in the plane of a resin layer by metal plating.
It is still another object of the invention to provide a multi-layer printed circuit board which includes bump vias filled with conductive material and having a planarized top face to allow higher density interconnection between the bump vias being stacked, and ensure higher interconnection reliability even where a bare chip is mounted on the bump vias.
In accordance with the present invention, there is provided a process for producing an inter-layer connection structure for interconnection between lower and upper electrical circuits, the process comprising the steps of: forming a resist pattern layer on a core circuit board including a substrate with a metal layer formed thereon; isotropically etching the metal layer to a selected depth by an etch down method to make a bump via; forming a lower pattern layer below the bump via by exposure and development of a positive resist and etching of the remaining metal layer; forming an insulating resin layer on the resulting board; and forming an upper pattern layer on the resulting board by polishing and roughening of the insulating layer and copper plating.
REFERENCES:
patent: 5092032 (1992-03-01), Murakami
patent: 5200026 (1993-04-01), Okabe
patent: 5219787 (1993-06-01), Carey et al.
patent: 5305519 (1994-04-01), Yamamoto et al.
patent: 5483984 (1996-01-01), Donlan, Jr. et al.
patent: 5738797 (1998-04-01), Belke, Jr. et al.
patent: 5883219 (1999
International Business Machines - Corporation
Jordan John A.
Perez-Ramos Vanessa
Samodovitz Arthur J.
Utech Benjamin L.
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