Inter-domain latch for scan based design

Details Inter-domain latch for scan based design Inter-domain latch for scan based design

1992-05-29

1995-02-14

Voeltz, Emanuel T.

Excavating

327141, 327291, 327199, 326 93, H04B 1700

Patent

active

053901908

ABSTRACT:
In a sequential logic design having two domains, each having opposing clock edge for its flip-flops, an inter-domain latch is provided for establishing a controllable and observable boundary point for the two domains. The inter-domain latch comprises three multiplexors and three latches. The first multiplexor, the first latch, the second multiplexor, the second latch, the third latch and the third multiplexor are coupled serially. Additionally, the output of the first latch is by-passed to the third multiplexor. The latches either open when the clock pulse is low or when the clock pulse is high. The first and third latches are driven by the same clock pulses, and the second latch is driven by an inverted clock pulse. Scan vectors for the first and second domains are scanned in through the first and second multiplexors respectively. The outputs of the first and second domains are observed at the second latch and the third multiplexor respectively.

REFERENCES:
patent: 5252917 (1993-10-01), Kadowahi
patent: 5281864 (1994-01-01), Hahn et al.

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