Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-26
2001-12-18
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S218000
Reexamination Certificate
active
06331953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of erasing multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitride-oxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
An attempt to improve the erasure of such ONO EEPROM devices is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of which are hereby incorporated herein by reference. In those disclosed devices, a cell is erased by applying a constant negative voltage to the gate over a plurality of cycles. However, the number of cycles and time to erase the memory cell can become large. Furthermore, the memory cell may become degraded should the number of cycles needed to erase the cell becomes too large. The slowing down of the erase speed is due to the trapping of electrons in the oxide layers or charge spill over into the nitride layer.
SUMMARY OF THE INVENTION
One aspect of the invention regards a method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
A second aspect of the present invention regards a method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes:
a) applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; b) detecting the current generated in response to the voltage applied in step a); and c) comparing the detected current of step b) with a predetermined threshold current value, wherein should the detected current vary from a predetermined erase verified current value by at least a predetermined amount, then steps a)-c) are repeated, and should the detected current vary from the predetermined erase verified current by an amount less than the predetermined amount, then a voltage is applied across the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.
Each of the above aspects of the present invention provides the advantage of a more efficient erasure of a memory cell in that the time to erase a cell is lessened.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
REFERENCES:
patent: 5414665 (1995-05-01), Kodama
Derhacobian Narbeh
Sobek Daniel
Wang Janet S. Y.
Advanced Micro Devices
Amin & Turocy, L.L.P.
Fears Terrell W.
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