Intelligent programmable dram interface timing controller

Details Intelligent programmable dram interface timing controller Intelligent programmable dram interface timing controller

1993-08-30

1996-06-25

Robertson, David L.

395432, G06F 103, G06F 1312

Patent

active

055309445

ABSTRACT:
The amount of user configuration required for a programmable DRAM interface controller is minimized while assuring adherence to DRAM signal specifications and providing improved DRAM memory transfer performance using a novel intelligent programmable DRAM interface controller which allows programming of TRAS, TRP, TRCD, TCP, TCAS and TCST in units of the cpu clock/2 while obtaining TCSH and TRSH specifications without explicitly programming these parameters. THE TCSH specification is accomplished by holding CAS from deasserting until RAS has deasserted or until the RAS programmed low time has been met. The TRSH specification is accomplished by holding RAS asserted in all normal read or write accesses for at least one time unit after CAS has been asserted, which, in a majority of CPU/DRAM Systems, insures that the DRAM limitation TRSH is satisfied.

REFERENCES:
patent: 5307320 (1994-04-01), Farrer et al.
patent: 5394541 (1995-02-01), Chesley et al.
patent: 5418924 (1995-05-01), Dresser

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