Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2000-02-16
2004-07-06
Harvey, Jack B. (Department: 2142)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S226000, C709S235000, C709S237000, C709S243000, C710S053000, C714S748000, C713S322000, C370S216000, C370S336000
Reexamination Certificate
active
06760781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer networks and to interface devices for connecting host computers to networks. More particularly the present invention relates to the retransmission of traffic by network interface cards (NICs) in network connected systems.
2. Description of Related Art
Computer systems that include network interfaces that support high speed data and status message transfers between a host computer and a data network are old. Local Area Networks (LANs) are a well known class of data network and are typically high speed networks constructed at low cost. Usage of low cost networks based on Carrier-Sense Multiple-Access with Collision Detection (CSMA/CD) techniques, such as Institute of Electrical and Electronic Engineers standard number 802.3 (IEEE 802.3) and ETHERNET(TM) is commonplace.
Typical implementation of ETHERNET and the like on popular Personal Computers (PCs) includes an adapter commonly termed a Network Interface Card (NIC). Such adapters typically connect to a PC via a bus such as the well known PCI, PCMCIA etc. NIC attachment to ETHERNET/IEEE 802.3 is according to one of the well known standards in the art, such AUI, 10Base2, 10BaseT, 100BaseT, various other 100 Megabit standards, or even Gigabit ETHERNET.
NICs typically have semiconductor read-write random access memory arrays (RAM) so that data transfers to and from the host memory are anisochronous to transfers to and from the LAN circuit or circuits. Such RAM is typically arranged as at least two first-in-first-out buffers (FIFOs). Thus, packets coming into the NIC, from the host memory, are stored in a first FIFO pending transmission onto the LAN. Conversely, packets coming into the NIC from the LAN are stored in a second FIFO, pending transfer into the host memory. The FIFO structure is a popular and efficient, high throughput system for managing high speed network interfaces. The efficiency and high throughput have come at the cost of flexibility in the operation of network interfaces. For example, once a packet has been downloaded to the interface, the host loses control over the processing of the packet. Thus, for example, if a host desires to send a packet repeatedly, the host process must manage repeated transmit requests. Also, if more than one process is sharing a network interface, then the contents of the FIFO in the network interface is unpredictable. Thus, schemes for downloading functions from the host to the network interface are difficult in high throughput environments using FIFO's or other network interface managed memory.
Accordingly, it is desirable to enhance the functionality of a network interface without sacrificing the high throughput efficiency of FIFO based, or other buffer architecture based, structures.
SUMMARY OF THE INVENTION
The present invention provides support for autonomous repeated transmission of data packets in a transmit buffer by a NIC. The present invention supports such retransmission by allowing commands from a host processor, or other source, for such purpose, without reducing the efficiency of the transmit path through the NIC. In addition an order to stop retransmission is provided.
One aspect of the present invention is a computer system that includes a host computer processor and a network interface apparatus having a first port coupled to the host processor and a second port adapted for transmitting data to a network. A buffer is coupled to the first and second ports and stores data packets from the first port. The buffer comprises a first-in-first-out buffer in one aspect of the invention. Logic based circuitry is included in the network interface. The circuitry responds to data and command signals from the host and stores packet data and other information in the buffer and, in preferred embodiments, in registers. The circuitry also transfers packets out of the buffer to the second port according to the information stored in the buffer and/or the registers so that certain packets may be repeatedly transmitted. Such retransmission is independent of retried transmissions that may be imposed by the MAC in response to collision conditions.
In one embodiment, the host processor generates a test packet of data, sometimes referred to as test patterns, as may be used for example to test NIC hardware in a manufacturing environment or for performance testing. The test packet is downloaded to the FIFO buffer in the NIC, along with a command to repeat transmission of the packet a number of times, or indefinitely until a stop command is issued by the host. When the test packet reaches the top of the FIFO, it is transmitted repeatedly without further host intervention. So even if the host powers down or crashes, the retransmission proceeds.
In another embodiment, different types of test packet are used with (1) autonomous retransmission by the NIC and (2) retransmission supervised by the host. This can help with isolating faults and other troubleshooting. A further utility is for separately or concurrently burning-in memory and analog components in the NIC such as part of an acceptance test. In a still further embodiment, failure conditions in the host may allow the host to command, for example, the perpetual retransmission of a “trap” message in accordance with Simple Network Management Protocol (SNMP), thus raising a network alarm condition even if the host were to shut down completely (assuming power is still available to the NIC). For information on the use of SNMP, see for example Internet Engineering Task Force Request for Comment 1213 (IETF RFC 1213).
Furthermore, the described embodiments operate in a manner that allows a NIC to operate with host device drivers that are unaware of the retransmission features so as to provide backwards compatibility at the host software, host hardware and the network interface levels.
REFERENCES:
patent: 5444718 (1995-08-01), Ejzak et al.
patent: 5487072 (1996-01-01), Kant
patent: 5841988 (1998-11-01), Chennubhotla et al.
patent: 6021124 (2000-02-01), Haartsen
patent: 6138189 (2000-10-01), Kalkunte
patent: 6163869 (2000-12-01), Langmann
patent: 6327625 (2001-12-01), Wang et al.
patent: 6389479 (2002-05-01), Boucher et al.
patent: 6393483 (2002-05-01), Latif et al.
patent: 6519223 (2003-02-01), Wager et al.
patent: 6546496 (2003-04-01), Wang et al.
10 pages from 3Com website entitled “Enhancing Enterprise Security”.
“10/100 Mbps Fast Ethernet PCI Network Interface Card 100 Mbps Performance Benchmark Comparison” by LanQuest Labs dated Jan. 1998 consisting of 4 pages.
10 pages from 3Com website entitles “3Com Corporation Fast EtherLink Server NIC (3C980-TX) Competitive Evaluation”.
4 pages from 3Com website entitled “Introducing the 3CR990-TX-97 10/100 PCI NIC with 3XP processor”.
2 pages from 3Com website entitled “3Com EtherLink 10/100 Mbps Desktop Network Interface Cards”.
2 pages from 3Com website entitled “Fast EtherLink Server Network Interface Card”.
Ho Ngo Thanh
Wang Chi-Lie
3Com Corporation
Harvey Jack B.
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Nguyen Hai V.
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