Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2003-12-05
2009-08-25
Tran, Philip B (Department: 2455)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S223000, C709S224000, C709S228000, C710S005000, C710S039000, C710S311000
Reexamination Certificate
active
07581033
ABSTRACT:
Intelligent NIC optimizations includes system and methods for Token Table Posting, use of a Master Completion Queue, Notification Request Area (NRA) associated with completion queues, preferably in the Network Interface Card (NIC) for providing notification of request completions, and what we call Lazy Memory Deregistration which allows non-critical memory deregistration processing to occur during non-busy times. These intelligent NIC optimizations which can be applied outside the scope of VIA (e.g. iWARP and the like), but also support VIA.
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Ebersole Dwayne E.
Inforzato Sarah K.
Johnson Robert A.
Narisi Anthony
Wild Kathleen
Gregson Richard J.
Marley Robert P.
Tran Philip B
Unisys Corporation
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