Intelligent memory system for processing varibable length I/O in

Details Intelligent memory system for processing varibable length I/O in Intelligent memory system for processing varibable length I/O in

1995-11-16

1996-12-31

Shah, Alpesh M.

Pulse or digital communications

Repeaters

Testing

375431, 364231, 364244, 364DIG1, G06F 1200

Patent

active

055903703

ABSTRACT:
A memory system contains one or more active storage elements. Each active storage element includes a memory element and a processing element associated with the memory element. The memory element contains microcode for implementing a specific function. A first bus connects the processing element to a host processor. A second bus connects the processing element to a peripheral.

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A. Asthana, C. Delph, H. V. Jagadish, and P. Krzyzanowski, "Towards a Gigabit IP Router" Journal of High Speed Networks, 1 (1992), 281-288, IOS Press.

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