Static information storage and retrieval – Interconnection arrangements
Patent
1996-01-23
1997-10-14
Nguyen, Viet Q.
Static information storage and retrieval
Interconnection arrangements
36523003, 36523006, 395405, G06F 1500
Patent
active
056778643
DESCRIPTION:
BRIEF SUMMARY
1. INTRODUCTION
The present invention relates to improvements in Intelligent Memory Devices (IMDs). Intelligent Memory Devices are memory devices capable of performing other functions independently of the host processor, in addition to storage of data. Besides standard read and write commands, they might support functions like shifting, adding, and searching of data held in their memory.
According to a first aspect, the present invention consists in a memory module for storing data, and having a memory array organised as a plurality of contiguous data word storage elements, an access system arranged to provide a plurality of access modes to the memory array, and an interface system arranged to interpret access requests delivered to the module via address, data and control lines and to provide control signals to the access system to select the required access mode, to provide address information to select the storage element or elements to be accessed, and to provide access to the selected storage element or elements, the interface and access systems being arranged to provide conventional read/write access to the memory array in response to a conventional read/write request to the memory module and to provide additional access modes which allow data to be operated on within the memory module independently of a host system to which the memory module is connected.
According to a second aspect the present invention consists in an address range decoding device for controlling selection of a range of addresses in a storage array, comprising first and second address input means, decoding logic means and a plurality of address selection outputs, there being one output for each address in the storage array, the address range decoding means being arranged to accept starting and ending address codes as said first and second address inputs respectively and the decoding logic being arranged to activate those outputs corresponding to the first and second input addresses and each address between the first and second input addresses to facilitate an operation on the data in the range of storage locations bounded by the starting and ending addresses.
According to a third aspect the present invention consists in an instruction decoding device for decoding a memory operation instruction, comprising address input means, read/write control signal input means, instruction decoding logic and one or more outputs arranged to indicate a data operation to which the instruction relates, the instruction decoding logic being arranged to set the one or more outputs depending upon relative values of the address and control signals presented to the input means.
According to a fourth aspect the present invention consists in an instruction decoding device for decoding an instruction indicating an operation to be performed on data in a storage array having a plurality of contiguous addressable storage locations, the device comprising first and second address input means, read/write control signal input means, instruction decoding logic, address range decoding logic, one or more instruction outputs arranged to indicate the operation to be performed and a plurality of address selection outputs, the instruction decoding logic being arranged to compare the first and second addresses and respective read/write control signals and to set the one or more instruction outputs depending upon the relative values of the address and control signals, the address range decoding logic being arranged to control the plurality of address selection outputs, there being one address selection output for each address in the storage array, the address range decoding logic being arranged to accept starting end ending address codes as said first and second address inputs and to activate those address selection outputs corresponding to the first and second input addresses and each address between the first and second input addresses to select a range of storage locations bounded by the starting and ending addresses which contain the data upon which the operation is to
REFERENCES:
patent: 4835733 (1989-05-01), Powell
patent: 5134711 (1992-07-01), Asthana et al.
patent: 5475631 (1995-12-01), Parkinson et al.
Klivans Norman R.
Nguyen Viet Q.
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