Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
1999-12-10
2001-11-27
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S017000, C438S405000, C438S626000, C438S631000, C438S791000, 43, C257S207000, C257S758000
Reexamination Certificate
active
06323113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of integrated circuit designs. More particularly, the present invention relates to gate layer filling on semiconductor substrates.
2. Description of the Related Art
In semiconductor processing, dummy fill patterns have been used in diffusion mask and metal mask to prevent dishing effects from chemical-mechanical polishing (CMP) and to minimize the effects of device-to-device variations in pattern density. For example, in conventional shallow trench isolation processes, N+ and P+ diffusion islands are isolated by oxide filled trenches. The formation of the shallow trench involves etching of the silicon trench patterns into a silicon trench and subsequently filling the trenches with a thick oxide layer. The oxide layer is then planarized by using processes such as CMP, resist etchback, or oxide etchback processes. In these cases, the polish rate or etch rate is a function of the pattern density, which is defined as the percentage of the area that is occupied by diffusion patterns.
In order to ensure a uniform removal of the oxide over an entire wafer or substrate, the pattern density should ideally remain relatively the same over all areas. To achieve the relatively uniform pattern density, the “white space” or field on the semiconductor substrate is often filled with dummy diffusion patterns. After filling the white space with the dummy fill patterns, circuit areas (e.g., dense diffusion patterns) and the field areas on the semiconductor substrate will have relatively similar pattern densities. It should be noted that the dummy fill patterns, also referred herein as fill pattern diffusion regions, are not used to form active semiconductor devices. Instead, the dummy fill patterns are used to produce a more even or consistent diffusion pattern density.
Dummy fill patterns are well known in the art and are described, for example, in U.S. Pat. No. 5,923,947, entitled “Method for Achieving Low Capacitance Diffusion Pattern Filling” and in U.S. Pat. No. 5,854,125, entitled “Dummy Fill Patterns to Improve Interconnect Planarity.” The disclosures of these patents are incorporated herein by reference.
In conventional applications, dummy fill patterns are often applied to open spaces over a semiconductor substrate so that a global pattern density of about 50% is typically achieved regardless of the original circuit design density. Unfortunately, while such an arrangement works reasonably well for diffusion and metal masks, it is generally not acceptable for a gate mask due to degradation of endpoint signal and polysilicon to oxide etch rate selectivity. For example,
FIG. 1A
is a graph showing a relationship between optical emission intensity at 520 nm from a polysilicon etch plasma as a function of etch time. In this graph, the endpoint signal strength, which is used to detect the endpoint of a polishing wafer, is shown to exhibit substantial variance depending on the polysilicon pattern density. In particular, the endpoint of a sparsely patterned polysilicon layer
102
differs substantially from the endpoint of a densely patterned polysilicon layer
104
.
On the other hand,
FIG. 1B
is a graph illustrating substantial variation of poly:oxide selectivity
110
as the percentage of digitization, which is the percentage of poly surface covered by a resist, varies. This variation results in lower selectivity for patterns with more resist. As shown, the poly:oxide selectivity drops off substantially as the digitization percentage increases from 0 to 50 percent.
Despite such drawbacks of the fill patterns in conventional gate masks, the dummy fill patterns are nevertheless used frequently for gate masks because they tend to reduce variations in polyline width or critical dimension (CD) such as electrical CD, effective channel length L
eff
, or the like. These variations generally result from device-to-device variations in global pattern density. For example,
FIG. 1C
shows a graph depicting the effect of varying gate pattern density on electrical critical dimension
112
and effective channel length
114
of an exemplary n-channel transistor. The range of pattern densities in this graph encompasses the range of typical design parameters used in conventional fabrication processes. As shown, the electrical critical dimension and the effective channel length L
eff
for the n-channel transistor are substantially dependent on the global pattern density at the gate layer. In particular, the overall variation attributable to the pattern density is shown to be about 25% for electrical critical dimension and about 10% for L
eff
. As can be appreciated by those skilled in the art, such significant variations are generally undesirable in semiconductor processing, especially in submicron processing.
Accurate control of the CDs and etch selectivity of polysilicon lines is generally of critical importance in the manufacturing of IC circuits as they affect the electrical characteristics of transistors. Precise control of these parameters is especially crucial for manufacturing application-specific ICs (ASICS) because ASICs typically exhibit a large variation in transistor density and layout.
Thus, what is needed is a method for defining and filling a gate layer targeted to a specified target pattern density so as to reduce variations in critical dimension while minimizing the degradation of endpoint signal and polysilicon to oxide selectivity.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing methods for intelligently filling polysilicon gate layer with dummy fill patterns to produce a specified target pattern density. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, program instructions in a computer readable medium, or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a method for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density. A gate layout defining gate areas on the gate layer is provided along with a diffusion layout defining active diffusion areas over a semiconductor substrate. For the gate layout, a pattern density is determined. Then, the areas not occupied by the gate areas and the diffusion areas are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns. Each predefined fill pattern has a plurality of dummy fill patterns and is associated with a pattern density within the provided range of pattern densities. Among the set of predefined fill patterns, a predefined fill pattern is selected for producing the target pattern density. Then, the gate layer is filled by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas. In so doing, the target pattern density is provided in the gate layer when combined with the pattern density of the gate layout.
In another embodiment, the present invention provides an automated method for identifying dummy fill locations in a gate layer to produce a target pattern density. The method includes: (a) providing a gate layout and a diffusion layout, the polysilicon gate layout defining gate regions and the diffusion layout defining diffusion regions over a semiconductor substrate; (b) determining a pattern density of the gate mask over the semiconductor substrate; (c) creating combined union regions of the gate and diffusion regions; (d) taking an inverse of the combined union regions for identifying regions not occupied by the gate and diffusion regions; (e) providing a set of predefined fill patterns associated with a range of pattern densities, each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the range of pattern densities; (f) iterating through the set of predefined fill pa
Bothra Subhas
Gabriel Calvin T.
Sur, Jr. Harlan L.
Zheng Tammy D.
Luu Pho
Martine & Penilla LLP
Philips Electronics North America Corporation
Zarabian Amir
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