Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit
Reexamination Certificate
2002-11-14
2004-11-16
Nguyen, Linh M. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Nonlinear amplifying circuit
C330S302000
Reexamination Certificate
active
06819168
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to circuits such as operational amplifiers (“op amps” or “op-amps”) for amplifying analog signals and in particular to CMOS operational amplifiers, and is more particularly directed toward a multi-stage integrator having high gain and fast transient response, for use in, e.g., op-amps.
BACKGROUND OF THE INVENTION
The conventional op amp, illustrated in
FIG. 1
in block diagram form, and generally depicted by the numeral
100
, comprises two analog, so-called linear amplification gain stages. The first functions as a differential transconductance (g
m
) stage
101
and the second as an integrator
103
, coupled by a differential to single-ended converter
102
(which may be incorporated into or merged with the transconductance stage. The conventional op amp
100
is illustrated in more detail in FIG.
2
.
As shown in
FIG. 2A
, the g
m
stage
101
comprises a differential pair
201
,
202
with a single current source “tail”
203
(both typically, and as an example, p-type insulated-gate field effect transistors—IGFETs), and two current source loads
204
,
205
(typically, and as an example, provided by n-type transistors). By selecting an output
206
from only one of the differential input stages, differential to single-ended conversion is accomplished; or, conventionally, current sources
204
and
205
are implemented as a mirror with single-ended output
206
derived from the high impedance side of the mirror.
This single-ended output
206
is then applied to the integrator stage
103
. In the implementation shown, the integrator
103
includes a n-type output transistor
207
with a current source tail
210
, and Miller capacitor
208
. A nulling resistor
209
has been added for the sake of stability.
In sub-micron CMOS technology, it is difficult to achieve an integrator with a combination of high gain and wide bandwidth with a high slew rate and a good transient response to high frequency events. The active devices are fast, but a single gain stage has very low DC gain. A multi-stage integrator (typically three inverting gains) gives high gain with simple (linear) inverting amplifiers, but must be stabilized with an internal nested pole; that sharply degrades the bandwidth, however, and thus results in a poor slew rate and poor transient response.
Another conventional rendering of the prior art operational amplifier of
FIG. 1
is shown at
250
in FIG.
2
B. In this type of circuit, all frequencies of an input signal V
in
applied differentially to the gates of transistors M
0
A and M
0
B pass through a conventional signal path comprising a first gain stage (the differential pair of transistors M
0
A and M
0
B) (which also yields differential-to-single-ended conversion) and a folded active cascode architecture integrator formed by transistors M
2
, M
3
and M
4
along with capacitor C
2
. The overall gain may be calculated to be, to a first approximation, (g
m
0*g
m
4*g
m
3*g
m
2)/(g
d
0*g
d
4*g
d
3*g
d
2), where g
m
x is the transconductance of transistor “Mx”; that is, the variation in their drain currents with respect to gate voltage; and g
d
y is the output conductance of transistor “My” or, in other words, the ratio of drain current change with respect to drain voltage.
Current sources I
0
-I
4
may be implemented in any preferred way. Since the output conductance of current source
14
is critical and must be very low, of course, it will conventionally be implemented as an actively cascoded PMOS current source. The overall gain, noted above, is the same as would result from a single differential transconductance stage followed by a three transistor gain in the integrator. This circuit has very high low frequency gain (i.e., an average gain of greater than 30 dB per stage is reasonable in small geometry CMOS, to give an overall gain of greater than 120 dB). However, it suffers from poor transient response due to the number of nodes in the signal path, each of which will have parasitic capacitance, causing a ringing transient response.
Consequently, a need arises for an integrator implementation that provides high gain and good transient response and is suitable for sub-micron CMOS manufacture, while offering simplicity of design and economy in overall circuit area.
SUMMARY OF THE INVENTION
These needs and others are addressed by the present invention, in which an integrator for an op-amp provides an amplifier which achieves a high small-signal gain on the order of 80 dB, wide (i.e., 200 MHz typical) bandwidth, and very clean transient pulse response. The integrator may be implemented in as few as three stages.
In accordance with one aspect of the invention, a high-gain, fast response amplifier comprises a first (high gain, analog) amplifier path including a plurality of amplifying stages and a first amplifier path output, and providing a relatively high gain to signals bellow a selected frequency; a second, wide-bandwidth, analog amplifier path having a common input with the first amplifier path, and including an amplifying stage and a second amplifier path output; and means (e.g., a resistor or a direct connection) interconnecting the first and second amplifier paths to form a composite amplifier having the common input as the input thereto and the output of the second amplifier path as the output thereof.
The first amplifier path may include first and second cascaded amplifying stages, while the amplifying stage in the second path may include a compensation network connected in feedback to improve stability. In a preferred form of the invention, the compensation network includes a capacitance connected in feedback around the first amplifier path.
A still further aspect is a high-gain, fast response amplifier comprising a first amplifier path including a plurality of amplifying stages between an input and a first amplifier path output, and providing a relatively high gain to signals below a selected frequency presented to said input; a second, analog amplifier path receiving-signals corresponding to those supplied to said input and including an amplifying stage (e.g., a single-stage amplifier) operatively connected between said input and a second analog amplifier path output; and means interconnecting the first and second amplifier paths to form a composite amplifier having said input as the input thereto and the output of the second, analog amplifier path as the output thereof. The amplifying stage in the second path may comprise a transconductor.
An additional feature is an integrator providing first and second signal paths between an integrator input and output. Such an integrator comprises the first signal path including multiple cascaded amplifying stages coupled between the integrator input and an amplifier output; the second signal path limited to a single transconductor stage coupled between integrator input and output; a capacitance coupled between the amplifier output and the integrator input; and the amplifier output and the integrator output being coupled such that the first signal path provides a relatively high-gain, narrow band amplifier, and a second signal path provides a relatively low-gain, broadband amplifier, and the first and second signal paths combine to form a single amplifying structure with relatively high low-frequency gain, and relatively fast high-frequency transient response.
Yet another aspect or feature is an improvement in an amplifier for use in driving capacitive load connected to the amplifier output node, such amplifier being of the type having an input transconductor stage followed by an actively cascoded integrator stage which has a cascode circuit receiving an output of said input stage and an output transistor driven by an output of the cascode circuit, the output transistor also being connected to a current source load at said output node. The improvement comprises the current source being a transistor having a control electrode connected to an input node of the cascode circuit; and a capacitance connected to restrict the bandwidth of the cascode circuit relati
Analog Devices Inc.
Nguyen Linh M.
Wolf Greenfield & Sacks P.C.
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