Integrator circuit

Details Integrator circuit Integrator circuit

1990-05-08

1991-06-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307353, 323316, G05F 324

Patent

active

050234897

ABSTRACT:
An integrator circuit which uses switched current techniques and includes a first current memory cell (T31,T32, S31, C31) a second current memory cell (T33, T34, C32, S32, T35) and a third (correcting) current memory cell (T36, S33, C33). An input current signal is fed to input (30) and a switch (S30) is closed during the .phi. portion of each sampling period, as is the switch (S31) in the first current memory cell. The other switches (S32, S33) are closed during the .phi. portion of each sampling period. During the .phi. portion transistor (T31) acts as a current source producing the current applied to it in the preceding .phi. portion. This is subtracted from the current produced by the output of the second current memory cell (T34) and the difference is stored in the third current memory cell (T36, S33, C33). During the next .phi. portion transistor (T36) acts a current source correcting the feedback current fed to the input (T31) of the first current memory cell. This reduces the sensitivity of the integrator to device matching.

REFERENCES:
patent: 4864217 (1989-09-01), Bird
patent: 4866368 (1989-09-01), Bird
patent: 4897596 (1990-01-01), Hughes

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