Integration of high voltage JFET in linear bipolar CMOS process

Details Integration of high voltage JFET in linear bipolar CMOS process Integration of high voltage JFET in linear bipolar CMOS process

2011-08-02

2011-08-02

Nguyen, Ha Tran T (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257SE29242, C257SE21400, C438S195000

Reexamination Certificate

active

07989853

ABSTRACT:
A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

REFERENCES:
patent: 2005/0173726 (2005-08-01), Potts

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