Integration of high performance submicron CMOS and dual-poly non

Details Integration of high performance submicron CMOS and dual-poly non Integration of high performance submicron CMOS and dual-poly non

1998-10-07

2000-07-11

Wojciechowicz, Edward

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

438 72, 438333, 438337, 257369, 257385, 257314, H01L 2934, H01L 2978

Patent

active

RE036777&

ABSTRACT:
An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.

REFERENCES:
patent: 5175120 (1992-12-01), Lee
patent: 5188976 (1993-02-01), Kume et al.
patent: 5194924 (1993-03-01), Komori et al.
F. Masuoka et al., "A 256-kbit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 4, Aug. 1987, pp. 548-552.

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