Integration of CMP and wet or dry etching for STI

Details Integration of CMP and wet or dry etching for STI Integration of CMP and wet or dry etching for STI

1999-04-29

2001-03-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S437000, C438S692000, C438S693000

Reexamination Certificate

active

06197660

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to shallow trench isolation and methods for filling said trenches.
BACKGROUND OF THE INVENTION
As the devices used in integrated circuits continue to shrink in size, the method of shallow trench isolation (STI) has been widely used in preference to the earlier method known as local oxidation of silicon (LOCOS). In practice, the dimensions of trenches that are to be filled can vary significantly. In particular, it is possible that some of the trenches may have very small widths, as low as about 3,000 Angstroms. Special deposition methods need to be used to fill such narrow trenches. An example of this is the method known as HDPCVD. (High density plasma chemical vapor deposition) wherein conventional CVD is combined with bias sputtering. In this manner, atoms or molecules that are not tightly bound are re-sputtered before they get incorporated into the growing film. The result is a very dense material comparable, in the case of deposited oxide, to an oxide layer grown by thermal oxidation.
In practice, it is always necessary to over-fill the trenches and to then etch back until the trenches have just been filled. This is not of itself a problem unless the surface between the trenches has been coated with a hard material such as, for example, silicon nitride.
FIG. 1
shows an example of such a situation. Silicon body
10
has an upper surface of silicon nitride
12
(underlaid by a thin layer of pad oxide for the purpose of stress reduction). Trenches
13
and
14
of different sizes have been etched into the surface of
10
.
FIG. 2
shows the result of covering silicon body
10
with a layer of HDPCVD oxide. All trenches have been over-filled so that there is an excess amount of layer
15
above the the silicon nitride.
The practice of the prior art would now be to use CMP to planarize the surface. Because of the hardness of the material directly above the silicon nitride as compared to material over the trenches, the appearance of the structure after CMP is as shown in FIG.
3
. As can be seen, considerable dishing
34
has occurred over the wider trench. Little or no dishing has occurred over the narrower trench
33
because the advance of the etch front will be dominated by the silicon nitride surface on each side. Thus, the problem which the present invention seeks to solve is how to combine the HDPCVD deposition method with the CMP material removal method.
In our search for prior art we came across a number of references to HDPCVD oxide, to CMP, and to etch-back but none of these describe the process of the present invention. Several of these references were of interest, however. For example Jain in two patents of a divisional (U.S. Pat. No. 5,494,854 February 1996 and U.S. Pat. No. 5,621,241 April 1997) describes using HDPCVD together with CMP in connection with planarizing dielectric deposited over metal wiring. Yano et al. (U.S. Pat. No. 5,721,173 February 1998) shows methods of planarizing shallow trenches by means of a selective etch back process. Wang et al. (U.S. Pat. No. 5,175,122 December 1992) show a process involving planarization and etch back as do Peschke et al. (U.S. Pat. No. 5,663,107 September 1997).
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for shallow trench isolation in the absence of dishing.
Another object of the invention has been that said process be effective for trenches formed in the presence of a hard surface such as silicon nitride, said trenches having a wide variation in their dimensions.
A still further object of the invention has been to integrate high density plasma CVD with CMP during trench filling.
These objects have been achieved by first over-filling trenches with a layer of HDPCVD oxide followed by the deposition of a relatively soft dielectric layer using a conformal deposition method. CMP is then used to remove both the added layer and most of the original HDPCVD oxide, a small thickness of the latter being left in place. Because of the earlier influence of the added layer the resulting surface is planar and a conventional wet or dry etch may be used to remove the remaining oxide, thereby exposing the top hard surface and filling the trenches without any dishing.


REFERENCES:
patent: 5175122 (1992-12-01), Wang et al.
patent: 5494854 (1996-02-01), Jain
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5621241 (1997-04-01), Jain
patent: 5663107 (1997-09-01), Peschke et al.
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5817567 (1998-10-01), Jang et al.
patent: 5872043 (1999-02-01), Chen
patent: 6037237 (2000-03-01), Park et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6136713 (2000-10-01), Chen et al.

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