Integrating I/O element

Details Integrating I/O element Integrating I/O element

1978-04-26

1980-01-15

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 100

Patent

active

041842006

ABSTRACT:
An integrating Input/Output (I/O) element containing an I/O processor that provides a computer with those functions normally associated with an I/O processor (or I/O controller) but which possesses architectural features to prevent compromise (i.e., unauthorized dissemination) of data in a multi-level secure environment. The I/O processor is programmable via an internal instruction memory which cannot be altered by the I/O processor and which cannot be accessed by any other portion of the computer (i.e., Central Processor Unit). The instruction memory is segmented providing a separate segment for each I/O channel. The instructions used to control each I/O channel are stored within the segment of instruction memory allocated to that I/O channel. A secondary memory, called the hand-off memory, is a read/write memory accessible by the Central Processor Unit (CPU) as well as the I/O processor. The hand-off memory is also segmented having a separate segment for each level of secure data to be stored within the hand-off memory. Each segment of the hand-off memory contains a subsegment allocated to each I/O channel permitted to handle the level of secure data associated with that segment of the hand-off memory. The control interface between the CPU and the I/O processor permits exchange of control and status information only. Therefore, all data transfers between the CPU and the I/O processor are via the hand-off memory. Because of the segmentation and subsegmentation of the hand-off memory, each such transfer is of a specific level of secure data and for a specific I/O channel.

REFERENCES:
patent: 3609697 (1971-09-01), Blevins
patent: 4031517 (1977-06-01), Hirtle
patent: 4034339 (1977-07-01), Free et al.

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