Integrating data scaling and buffering functions to minimize mem

Details Integrating data scaling and buffering functions to minimize mem Integrating data scaling and buffering functions to minimize mem

1997-07-03

2000-07-18

Saras, Steven J.

Computer graphics processing and selective visual display system

Computer graphics processing

Graph generating

345131, 348581, G09G 500

Patent

active

060914262

ABSTRACT:
A scaling circuit residing on a single silicon substrate includes a buffer for storing a plurality of partially scaled data. A multiplier is provided for multiplying a weight signal with each of a plurality of input data to produce a plurality of weighted data. An adder is coupled to (1) the multiplier and (2) the buffer for adding each of the weighted data to one of the partially scaled data to produce a plurality of scaled data. When a first one of the scaled data is produced by the adder, the first one of the scaled data can remain in the buffer until displaced by a new data to be scaled such that the scaling circuit is directly coupled to an external bus without requiring any external buffering memory coupled in between. A method for scaling a block of data and transferring the scaled data to the bus is also described.

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