Integrating chip scale packaging metallization into...

Details Integrating chip scale packaging metallization into... Integrating chip scale packaging metallization into...

2005-07-12

2005-07-12

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S773000

Reexamination Certificate

active

06917105

ABSTRACT:
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.

REFERENCES:
patent: 6498396 (2002-12-01), Arimoto
Dr. Luu Nguyen et al, Assembly Considerations for micro SMD Wafer-Level CSPs, Chip Scale Review, May/Jun. 2000, p. 48 et seq.
James L. Young, Wafer-Level Processing:—Working Smarter, Chip Scale Review, May 1997, p. 28 et seq.
Dr. Philip Garrou, Wafer-Level Packaging Has Arrived, Semiconductor International, Oct. 2000, p. 119 et seq.

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