Integrating analog/digital converter

Details Integrating analog/digital converter Integrating analog/digital converter

2001-01-16

2001-09-04

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S167000, C341S157000, C341S155000, C341S168000, C341S169000, C341S170000, C341S128000, C341S129000, C341S118000

Reexamination Certificate

active

06285310

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to an integrating analog/digital converter. In general, such analog/digital converters include: an amplifier wired as an integrator, a comparator provided downstream from the integrator, a time counter which continually counts the pulses of a pulse generator, and a bistable element. The bistable element drives the input network of the amplifier with at least one switch in such a way that in one of its two positions (“off” condition) a current I
x
proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current I
ref
with opposite polarity to I
x
is added to I
x
and both are integrated. The switching of the bistable element from the “off” condition to the “on” condition is controlled by the time counter; and the switching from the “on” condition to the “off” condition (switch-off time) is controlled by the output signal of the comparator, which is generally synchronized with the pulses of the pulse generator. The pulses of the pulse generator are summed to a result during the time the bistable element is in its “on” position.
BACKGROUND OF THE INVENTION
Analog/digital converters of this type are known from U.S. Pat. Nos. 3,765,012, 4,361,831, and 5,262,780.
A circuit diagram of this so-called multiple ramp procedure is depicted in FIG.
1
. In addition,
FIG. 2
depicts the time trace of the voltage V
C
at the integration capacitor C and/or at the output
11
of the integrator
1
, for explaining the method of operation.
The current I
x
to be measured is continuously supplied to the input
10
of the integrator
1
. If the analog/digital converter is used as a voltage meter, the measurement voltage is converted via a fixed resistor into a measurement current I
x
. At certain times, the switch
3
is closed and the input
10
of the integrator
1
is additionally supplied with a fixed reference current I
ref
of polarity opposite that of I
x
. The reference current I
ref
can, for example, be produced from a Zener diode (=reference voltage) and a fixed resistor. For illustrating the temporal sequence in
FIG. 2
, it is assumed that I
x
is negative and I
ref
is positive. Starting from a voltage level zero at the integration capacitor C at time t
1
in
FIG. 2
, the switch
3
is open during the period T
1
, and the voltage V
C
at the output
11
of the integrator
1
increases proportionally to I
x
. After the time T
1
, this voltage reaches the value:
V
0
=
-
I
x
C
·
T
1
(
1
)
At time t
2
in
FIG. 2
, the switch
3
is closed. Since I
ref
>−I
x
, the influence of I
ref
now predominates, and the voltage V
C
falls until it reaches the value zero again at time t
3
. The following equation then applies for the charge balance:
-
I
x
C
·
T
1
=
V
0
=
I
x
+
I
ref
C
·
T
2
(
2
)
After appropriate transformation, one obtains:
I
x
I
ref
=
-
T
2
T
1
+
T
2
=
-
T
2
T
(
3
)
If T
1
+T
2
=T=constant and I
ref
=constant, then T
2
is directly proportional to the current I
x
to be measured.
In the circuit of
FIG. 1
, the switch
3
is driven by a bistable element
4
which closes the switch
3
in its “on” condition and opens the switch
3
in its “off” condition. The switching to the “on” position at the times t
0
, t
2
, t
4
etc. in
FIG. 2
results from the overflow signal of a time counter
6
on the line
12
. The time counter
6
continuously counts the pulses of a pulse generator
5
, so that the overflow signal appears at regular time intervals. This allows the condition T
1
+T
2
=T=constant to be realized. The switching of the bistable element
4
back into the “off” condition at the times t
1
, t
3
etc. in
FIG. 2
results from the output signal of the comparator
2
(line
13
) upon reaching the zero line of the integrator voltage at point
11
in FIG.
1
. If the switch
3
is closed, a gate
8
is opened via a line
14
, so that, during the time T
2
, the pulses of the pulse generator
5
are registered in a result counter
7
. This pulse count proportional to T
2
is thereby, according to equation (3), also proportional to the current I
x
to be measured, since T and I
ref
are constant. The microprocessor
9
in
FIG. 1
also receives the comparator signal via line
15
. Following the next pulse of the pulse generator (which is simultaneously the clock unit for the microprocessor
9
in FIG.
1
), the microprocessor can read out the value of the result counter
7
and output and/or further process this value as the measurement result of a single measurement cycle. The result counter
7
is reset to zero via the line
16
at the times t
0
, t
2
, t
4
etc.
In the circuit of
FIG. 1
, it is further provided that the opening of the switch
3
does not occur in synchronization with the comparator signal on the line
13
, but only with the next pulse of the pulse generator
5
(synchronization input
60
on the bistable element
4
). The equation (2) thereby is only approximate for each measurement cycle. However, the small deviations are transferred in analog form to the next measurement cycle, so that this error cancels out over several measurement cycles. Switching in synchronization with the pulse of the pulse generator
5
has the great advantage that T
1
as well as T
2
are always exact multiples of the clock period of the pulse generator
5
, so that no rounding errors can add up during the adding/averaging of several measurement cycles. A total result with N-fold resolution results from the sum—or the running sum—and/or the average of N measurement cycles. The practical resolution is limited only by the quality of the components used.
The multiple ramp process is described only briefly in the preceding passages. Particulars can be found in the patent specifications already cited.
Advantages of this process include:
The current I
x
is not switched; therefore there is no influence from current/voltage-dependent switching capacities of the switch;
The size of the integration capacitor C does not enter into the calculated result, as evident from equation (3);
Through averaging and/or summation over N measurement cycles, the resolution of the analog/digital converter can be increased in correlation to the number N;
The measurement results are available in a fixed time slot pattern, so that further averaging, calculation of rates of change, etc., are made easier.
This known process has the disadvantage, however, that after a change in current I
x
at the input, the pulses summed in the result counter only gradually converge to the correct final value and do not converge at all for values of |I
x
/I
ref
|>1/2.
This is to be explained in greater detail with reference to FIG.
3
. Several sequential up-integrations and down-integrations are depicted here, just as in FIG.
2
. The theoretical voltage trace at the capacitor C (in
FIG. 1
) in steady state condition is indicated with a dashed line; the actual voltage trace which occurs, for example, after a disturbance or after a sudden voltage change at the input (in which case the down-integration at time t
0
starts with a value which deviates from the steady state condition by a value x
0
) is indicated with a solid line. The time error that thereby arises in the first down-integration is s
1
, the time error arising in the second down-integration is s
2
, etc.
Due to the parallel relationship of the two straight lines
17
and
18
, one obtains, from the intercept theorems:
s
1
T
1
=
x
1
V
0
(
4
)
And, analogously, due to the parallel relationship of the two straight lines
19
and
20
:
&LeftBracketingBar;
s
2
&RightBracketingBar;
T
2
=
x
1
V
0
(
5
)
By elimination of V
0
, one thus obtains:
&LeftBracketingBar;
s
2
&RightBracketingBar;
=
T
2
T
1
·
s
1
(
6
)
If one considers that s
2
and s
1
have different signs and one generalizes equation (6) to the error s
n
, one obtains:
s
n
=
-
T
2
T
1
·
s
n
-
1
(
7
)
One recognizes from this that, after a disturbance, the time error s
n

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