Integrated XOR/multiplexer for high speed phase detection

Details Integrated XOR/multiplexer for high speed phase detection Integrated XOR/multiplexer for high speed phase detection

2002-04-30

2003-05-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By phase

C327S099000, C327S411000, C326S052000

Reexamination Certificate

active

06566912

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to digital and analog circuit design. More particularly, the present invention relates to a digital circuit that combines the functionality of an XOR gate in series with a multiplexer.
BACKGROUND OF THE INVENTION
High speed digital data communication devices utilize phase detector circuits to produce an output voltage proportional to the frequency or phase differences of two input signals. During frequency acquisition, the frequency of an incoming data signal is compared to the frequency of an external reference clock. During phase acquisition, incoming data is compared to a derived version of an internal reference clock (usually generated by a voltage controlled oscillator).
FIG. 1
is a block diagram of a prior art digital circuit
100
that may be utilized in a phase detector application. Circuit
100
includes an XOR component
102
and a multiplexer
104
connected in series with XOR component
102
. One input to XOR component
102
represents a first half-rate data signal
106
based upon an input data signal (not shown), and the other input to XOR component
102
represents a second half-rate data signal
108
based upon the input data signal. In this regard, one input to XOR component
102
includes the “odd” data bits from the input data signal and the other input to XOR component
102
includes the “even” data bits from the input data signal. The output of XOR component
102
represents a phase detect signal
109
. Circuit
100
also receives a frequency detect signal
110
from a frequency detection circuit (not shown) and a frequency lock signal
112
(frequency lock signal
112
serves as a selection signal for multiplexer
104
). Ultimately, circuit
100
generates an output signal
114
—the output of multiplexer
104
.
Circuit
100
utilizes output signal
114
to adjust the frequency and phase of a clock signal
116
generated by a voltage controlled oscillator (VCO)
118
. Initially, circuit
100
selects frequency detect signal
110
(using multiplexer
104
) for use as output signal
114
, which controls the operation of VCO
118
such that the frequency of clock signal
116
matches the frequency of a reference clock signal, which corresponds to the frequency of the incoming data signal. Thereafter, circuit
100
selects phase detect signal
109
(using multiplexer
104
) for use as output signal
114
, which controls the operation of VCO
118
such that the phase of clock signal
116
is properly aligned relative to the phase of the input data signal.
FIG. 2
is a schematic representation of circuit
100
as implemented in a practical device. In a practical high speed application, circuit
100
handles differential input signals and generates a single ended output signal
114
. Accordingly, first XOR input signal
106
is represented by a positive or “true” signal (IN
AP
) and a negative or “complementary” signal (IN
AN
), second XOR input signal
108
is represented by a positive signal (IN
BP
) and a negative signal (IN
BN
), and phase detect signal
109
is represented by a positive signal (XOR
P
) and a negative signal (XOR
N
). Likewise, frequency detect signal
110
is represented by a positive signal (FD
P
) and a negative signal (FD
N
), and frequency lock signal
112
is represented by a positive signal (SEL
P
) and a negative signal (SEL
N
).
Circuit
100
is implemented such that the transistors, resistors, and other features of XOR component
102
are physically distinct from the transistors, resistors, and other features of multiplexer
104
. In this regard,
FIG. 3
is a schematic of a prior art XOR component
300
, and
FIG. 4
is a schematic of a prior art multiplexer
400
. XOR component
300
is designed to operate as an independent device that generates a differential XOR output
302
based upon two differential input signals
304
/
306
, and multiplexer
400
is designed to operate as an independent device that selects an output signal
402
from two differential input signals
404
/
406
based upon the state of a differential select signal
408
. Referring back to
FIG. 2
, in a practical implementation, XOR component
102
is physically connected to multiplexer
104
using conductive traces configured to carry phase detect signal
109
between the components.
Circuit
100
, while suitable for relatively low speed data communication applications (e.g., those handling data rates of 2.5 Gbps or less), is not suitable for relatively high speed applications (e.g., those handling data rates up to or beyond 40 Gbps). In very high speed applications, the limited bandwidth of circuit
100
adversely affects its performance. Furthermore, circuit
100
requires separate current sources (one or more for XOR component
102
and one or more for multiplexer
104
), which results in an inefficient use of operating power.
BRIEF SUMMARY OF THE INVENTION
A digital circuit according to the present invention includes the functionality of an XOR component integrated with the functionality of a multiplexer. The combined function of the digital circuit is equivalent to a distinct XOR component connected in series with a distinct multiplexer. The integrated configuration enables the circuit to achieve higher bandwidth than equivalent prior art circuits, while using less operating power.
The above and other aspects of the present invention may be carried out in one form by an integrated XOR/MUX device having: an XOR arrangement having a first collector node, a second collector node, and a first common emitter node, where the XOR arrangement is configured to perform an XOR operation on a first differential input signal and a second differential input signal; a first differential transistor pair having a second common emitter node connected to a current source, a third collector node connected to the first common emitter node, and a fourth collector node, where the first differential transistor pair is configured to receive a differential select signal; and a second differential transistor pair having a third common emitter node connected to the fourth collector node, a fifth collector node connected to a reference voltage node, and a sixth collector node connected to the first collector node, where the second differential transistor pair is configured to received a third differential input signal.


REFERENCES:
patent: 3639781 (1972-02-01), Marley
patent: 4628216 (1986-12-01), Mazumder
patent: 4831579 (1989-05-01), Hara et al.
patent: 5252865 (1993-10-01), Davenport et al.
patent: 5260952 (1993-11-01), Beilstein, Jr. et al.
patent: 5315176 (1994-05-01), Popescu
patent: 5801571 (1998-09-01), Allen et al.
patent: 5909127 (1999-06-01), Pearson et al.
patent: 6008670 (1999-12-01), Pace et al.
patent: 6137309 (2000-10-01), Couteaux et al.
patent: 6194917 (2001-02-01), Deng
patent: 6414519 (2002-07-01), Abernathy
patent: 6424194 (2002-07-01), Hairapetian

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