Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1998-02-12
2001-02-13
Lee, Thomas C. (Department: 2782)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S505000, C370S506000, C370S476000, C370S399000, C331S011000, C331S057000, C710S106000
Reexamination Certificate
active
06188692
ABSTRACT:
FIELD
The present invention relates to a monolithic integrated circuit that interface between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) STS-3c, which is a digital transmission standard that defines a new digital hierarchy for fiber optic transmission and a frame structure for multiplexing digital traffic, and asynchronous transfer mode (ATM). ATM is a new payload multiplexing technique which segments payload into 53-byte cells which can be allocated to user channels based on demand.
BACKGROUND
The advent of applications such as network computing, multimedia, video conferencing, and real-time imaging require data rates ranging into the gigabits-per-second. The demand for such high rates has led the industry to combine a standardized wide band network (SONET) with the simplicity of an efficient network that uses fixed-length 53-byte-wide asynchronous transfer-mode (ATM) cells. In 1992 ATM was chosen by the CCITT (Consultative Committee for International Telephony and Telegraphy and now the ITU) as the transport technology for the huge variety of services to be offered by the Broad band Integrated Services Digital Network (B-ISDN). However, it has been recognized that ATM is equally well-suited for use in the local area network. An ATM cell consists of 53 octets or bytes with a 5 byte cell header containing control bits and a 48 octet or byte cell payload which contains the data bits. In order to interface with a standardized wide band network, such as Synchronous Optical Network (SONET), appropriate interfaces to transfer from one system to the other have been and are being developed.
In order to integrate all of the functions of an ATM physical layer interface into a single device, and at the same time be applicable to local and wide area networking applications, a number of criterion have to be met. First, one requires a fully compliant SONET/SDH STS-3c framer. Here the term SDH refers to ITU's synchronous digital hierarchy and STS-3c refers to a data transmission rate of 155.52 megabits-per-second (Mbits/s) . The SONET STS-3c frame structure consists of 9 rows of bytes with each row having 9 bytes of transport overhead and 261 columns of 9 bytes each with one of the columns having control bits defining path overhead while the remaining columns are payload. The framer takes ATM cells and puts them into a synchronous series of SONET frames.
A second requirement of an interface device is an ATM cell processor to perform cell delineation and null cell insertion/filtering. Since many of the services elivered by ATM are by definition asynchronous, they are characterized by a non-continuous cell stream. Thus, cell rate de coupling transforms a non-continuous cell stream into a continuous stream by inserting idle or null cells (containing no payload) during idle periods in the assigned cell stream. By making the cell rate continuous, it is necessary only to synchronize with the incoming cells in order to place the ATM cells in their assigned locations in a frame.
A third requirement is a line side interface to support serial input/output at 155 Mbits/s. For SONET/SDH systems, current devices utilize expensive external phase locked loops and crystal oscillators to provide the clock recovery and clock synthesis functions. No one to date has been able to successfully implement integral phased locked loop circuits to recover clock and data from the encoded incoming data stream and to synthesize the high speed transmit clock from a low frequency reference.
Accordingly, it is an object of the invention to provide an integral phase locked loop that recovers the clock and data from the serial encoded receive stream and that synthesizes the high speed 155.52 MHz or 51.84 MHz transmit clock from a low frequency reference.
SUMMARY OF THE INVENTION
According to the invention there is provided a user network interface (UNI) device for interfacing between a synchronous optical network (SONET) and an asynchronous transfer mode (ATM) network. The UNI device has a transmit section and a receive section. The transmit section is operative to receive an incoming non-continuous stream of data cells from the ATM network, generate and insert idle cells into the incoming non-continuous stream of data cells to form a continuous stream of cells, map the continuous stream of cells into frames of data, and synchronously transmit the frames of data in an outgoing continuous stream of data. The receive section is operative to receive incoming frames of data in an incoming continuous stream of data, extract ATM cells from the incoming frames of data, and transmit the extracted ATM cells in an outgoing non-continuous stream of data cells. The receive section includes an integral clock recovery circuit operative to sample and recover clock from the incoming continuous stream of data.
The integral clock recovery circuit is preferably operative to lock on to and recover the clock from the incoming continuous stream of data when a frequency difference between a divided down output from the integral clock recovery circuit and a first reference clock signal is less than or equal to a predetermined threshold, and where otherwise the integral clock recovery circuit locks on to the first reference clock signal.
The integral clock recovery circuit is also preferably operative to lock on to and recover the clock from the incoming continuous stream of data only if the incoming continuous stream of data has a number of transitions greater than or equal to a preset value for an n-bit interval. In one embodiment, the preset value is 1 and the n-bit interval is an 80-bit interval.
Preferably, the integral clock recovery circuit includes a first voltage control oscillator (VCO) operative to lock on to the incoming continuous stream of data, a phase/frequency detector operative to compare the phase and frequency of a first reference clock signal and the divided down VCO output signal from a first divider circuit, and a data phase detector operative to compare the phase of the incoming continuous stream of data and the divided down output signal from the first divider circuit. Preferably, the first VCO is switched from the phase/frequency detector to the data phase detector when a frequency difference between a frequency of the divided down output signal from the first VCO and that of the first reference clock signal is less than or equal to a predetermined threshold, and the first VCO is switched back to the phase/frequency detector when the frequency difference exceeds the predetermined threshold.
The integral clock recovery circuit may include a first reference clock input line for receiving a first reference clock signal and a data input line for receiving the incoming continuous stream of data. The clock recovery circuit may also include a first loop filter operative to cut out high frequency components of input signals and to control input of the first VCO, a loop control multiplexer operative to selectively drive the loop filter and control the first VCO from one of the phase/frequency detector and the data phase detector, a transition detector operative to monitor a transition density of the incoming continuous stream of data, a clock difference detector, operative to compare a frequency of the first reference clock signal and the divided down output signal of the first VCO, and a control state machine operative to control the control loop multiplexer.
As contemplated within the scope of this invention, there is also provided a user network interface device comprising a transmit section and receive section wherein the receive section includes an integral clock synthesis circuit operative to synthesize a high speed transmit clock from a low frequency reference source. Preferably, the integral clock synthesis circuit includes a second voltage control oscillator (VCO); a second divider circuit having an input coupled to an output of the second VCO; (cc) a second loop filter having an output coupled to an input of the second VCO; (dd) a charge pump coupled to the second loop filter and operativ
Bradshaw John R.
Gerson Brian D.
Huscroft Charles K.
Little Vernon R.
Smith Graham B.
Hall Priddy Myers & Vande Sande
Lee Thomas C.
Peyton Tammara
PMC-Sierra Ltd.
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