Integrated trench-transistor structure and fabrication process

Details Integrated trench-transistor structure and fabrication process Integrated trench-transistor structure and fabrication process

1988-06-13

1989-11-14

James, Andrew J.

357 42, 357 46, 357 49, 357 55, 357 72, 357 54, H01L 2708, H01L 2978

Patent

active

048811050

ABSTRACT:
An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

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