Integrated thin film capacitor/inductor/interconnect system...

Details Integrated thin film capacitor/inductor/interconnect system... Integrated thin film capacitor/inductor/interconnect system...

2001-09-21

2004-07-13

Lam, Cathy (Department: 1725)

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

C428S210000, C174S257000, C174S258000, C361S750000, C361S751000, C361S765000, C361S766000, C361S792000, C361S794000, C361S795000, C361S811000, C361S812000, C363S147000

Reexamination Certificate

active

06761963

ABSTRACT:

PARTIAL WAIVER OF COPYRIGHT
All of the material in this patent application is subject to copyright protection under the copyright laws of the United States and of other countries. As of the first effective filing date of the present application, this material is protected as unpublished material.
However, permission to copy this material is hereby granted to the extent that the copyright owner has no objection to the facsimile reproduction by anyone of the patent documentation or patent disclosure, as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable
FIELD OF THE INVENTION
The present invention provides a system and method for fabricating high reliability capacitors, inductors, and multi-layer interconnects on hybrid microelectronic substrate surfaces using thin film technology. Specifically, it employs a thin lower electrode layer under a patterned dielectric layer. Conventional thin film conductors, upper electrodes for capacitors, spiral inductors, and resistor elements are then deposited on top of the dielectric layer to form thin film hybrid microelectronic devices containing conductors, capacitors, inductors, and resistors all integrated together on the same device.
BACKGROUND OF THE INVENTION
Hybrid microelectronic devices are manufactured on a variety of substrate materials using various techniques such as thick film, low temperature co-fired ceramic (LTCC), specialty printed circuit board (PCB), or thin film technology. Hybrid devices are used in many microelectronics applications in the defense, medical, communications, computer, automotive, and infrared imaging industries, as well as in many other applications. In all of these industries there is continuous demand for devices that offer improved performance and function. In order to satisfy these demands, the number of passive devices (capacitors, inductors, and resistors) designed into microelectronic devices continues to grow. For instance, a typical cellular phone product may contain 400 components with less than 20 devices being active (i.e., semiconductors) and the 380 or more devices being passive devices.
Along with demands for better performance are also requirements to provide products that are less expensive and smaller in size. It is reported that the passive components in a cellular phone product can occupy 80% of the printed circuit board area and account for 70% of the product assembly costs. Thus, there is clear need to reduce the size and cost of the passive devices required in microelectronic devices.
Of the hybrid circuit fabrication techniques, thin film technology is extremely well suited for use in RF/microwave, wireless, and optical transmission technologies because of its ability to provide high quality features, extremely dense packaging, and a large range of integrated features.
The current state of the art in thin film hybrid microelectronic manufacturing offers cost effective, high reliability methods for integrating conductors, inductors, and resistors onto the same thin film hybrid circuit device but not capacitors and interconnects (i.e. connections between devices and multiple layers).
Presently, capacitors are typically purchased individually and attached to the thin film devices using various surface mount die attach techniques. The individual chip capacitors take up valuable space, require much assembly labor, and can decrease reliability due to assembly problems.
Interconnects are often required to interconnect components and devices and to attach to the center of spiral inductors and power splitters such as Lange couplers. Current technology uses wire or ribbon bonding to make individual interconnects. Wire or ribbon bonds can add higher costs and sometimes cause high frequency performance problems due to bond inconsistencies, different bond shapes or the bonds falling over and shorting to conductor lines that they are crossing over.
Thus, there is a clear need for a reliable fabrication method that offers both integrated capacitors and integrated interconnects. It is especially desirable that this method provides features that are usable from DC to very high operating frequencies. The prior art does not satisfy this need.
A recent approach to the integration of capacitors and interconnects has concentrated on fabricating these devices on silicon wafers. See MARC DE SAMBER, NICK PULSFORD, MARC VAN DELDEN, ROBERT MILSOM; “Low-Complexity MCM-D Technology with Integrated Passives for High Frequency Applications”, The International Journal of Microcircuits and Electronic Packaging, Volume 21, Number 2, Second Quarter 1998, pgs 224-229 (ISSN 1063-1674) (International Microelectronics and Packaging Society).
This paper presented simple concepts for fabricating integrated capacitors, inductors, resistors, and interconnects on silicon wafers. However, processing thin film hybrid substrates offers unique challenges when compared to silicon wafers, and the teachings presented in this prior art are not directly applicable to thin film hybrid substrate processing.
DESCRIPTION OF THE PRIOR ART
Overview
Two basic techniques have been used in the past to fabricate integrated capacitors onto thin film hybrid devices. Both techniques are based on the “parallel plate” construction or MIM (metal-insulator-metal) capacitor design. Both techniques are inherently difficult to manufacture as they need to address the issue of “step coverage” of the dielectric layer over the thick bottom electrode.
PARALLEL PLATE CAPACITOR WITH STEP COVERAGE (
0100
)
FIG. 1
(
0100
) illustrates a MIM technique whereby a thin lower electrode (
0102
) is deposited and patterned on a substrate (
0101
). This lower electrode (
0102
) is then oxidized or anodized to form a thin oxide layer (
0103
) on its top surface that then becomes the dielectric layer in the capacitor. An upper electrode layer (
0104
) is then deposited and patterned on top of the insulator layer (
0101
) to form a MIM capacitor.
This type of capacitor is very difficult to manufacture as it presents many problems such as capacitance value reproducibility problems, shorting (
0106
) of the top electrode (
0104
) to the bottom electrode (
0102
) through the thin dielectric (
0105
), low breakdown voltage, low Q (quality factor) at high frequencies, and wire bonding challenges.
The capacitor value or capacitance is inversely proportional to the thickness of the dielectric layer so it is very advantageous to have the dielectric layer as thin as possible. When depositing a thin dielectric layer over a thicker electrode layer electrical shorts are introduced at the edge (
0106
) of the bottom electrode (
0102
) due to poor “step coverage” (
0105
) of the dielectric layer (
0103
) as shown in
FIG. 1
(
0100
).
Air-Bridge Capacitor (
0200
)
FIG. 2
(
0200
) illustrates a MIM technique that uses a thick bottom electrode (
0202
), a dielectric layer (
0203
), and air-bridges (
0204
,
0205
,
0206
) to crossover to the upper electrode layer (
0207
). This technique uses multiple deposition and patterning processes to build up and then cross over to the upper electrode layer (
0207
).
This process is inherently difficult because the lower electrode (
0202
) is relatively thick, thereby making it problematic to make contact to the upper electrode (
0207
) without shorting to the thick lower electrode (
0202
). Most dielectric coatings (
0203
), in order to be applied at a thickness that will completely cover the lower electrode layer (
0202
), exhibit extremely low capacitance densities and therefore are used only rarely. Therefore, the air-bridge method becomes a logical method for making a connection to the upper electrode (
0207
) because it can use thinner dielectrics with higher capacitance densities.
This method exhibits manufacturing and repeatability problems due to its very complex nature. It is extremely expensive and problematic to produce

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