Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2008-06-24
2010-11-09
Sefer, A. (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S675000, C257SE23087, C438S122000
Reexamination Certificate
active
07830000
ABSTRACT:
Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
REFERENCES:
patent: 4640010 (1987-02-01), Brown
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5250843 (1993-10-01), Eichelberger
patent: 5353498 (1994-10-01), Fillion et al.
patent: 5841193 (1998-11-01), Eichelberger
patent: 5998859 (1999-12-01), Griswold et al.
patent: 6064114 (2000-05-01), Higgins, III
patent: 6159767 (2000-12-01), Eichelberger
patent: 6426545 (2002-07-01), Eichelberger et al.
patent: 6507115 (2003-01-01), Hofstee et al.
patent: 6555908 (2003-04-01), Eichelberger et al.
patent: 6586827 (2003-07-01), Takeuchi et al.
patent: 6818544 (2004-11-01), Eichelberger et al.
patent: 6838776 (2005-01-01), Leal et al.
patent: 6972964 (2005-12-01), Ho et al.
patent: 7006359 (2006-02-01), Galvagni et al.
patent: 7112467 (2006-09-01), Eichelberger et al.
patent: 7122467 (2006-10-01), Lee et al.
patent: 7238602 (2007-07-01), Yang
patent: 7339279 (2008-03-01), Yang
patent: 7345365 (2008-03-01), Lee et al.
patent: 7405102 (2008-07-01), Lee et al.
patent: 7427812 (2008-09-01), Wakisaka et al.
patent: 7429793 (2008-09-01), Yamagata
patent: 7550830 (2009-06-01), Yoon
patent: 7550833 (2009-06-01), Mihara
patent: 7572681 (2009-08-01), Hoemoeller et al.
patent: 7619901 (2009-11-01), Eichelberger et al.
patent: 2003/0197285 (2003-10-01), Strandberg et al.
patent: 2003/0201534 (2003-10-01), Eichelberger et al.
patent: 2005/0062147 (2005-03-01), Wakisaka et al.
patent: 2005/0161799 (2005-07-01), Jobetto
patent: 2006/0017155 (2006-01-01), Wang
patent: 2007/0249102 (2007-10-01), Brunnbauer et al.
patent: 2008/0315375 (2008-12-01), Eichelberger et al.
patent: 2008/0315377 (2008-12-01), Eichelberger et al.
patent: 2008/0315391 (2008-12-01), Eichelberger et al.
patent: 2010/0031500 (2010-02-01), Eichelberger et al.
patent: 2010/0032091 (2010-02-01), Eichelberger et al.
patent: 2010/0035384 (2010-02-01), Eichelberger et al.
patent: 2010/0044855 (2010-02-01), Eichelberger et al.
patent: 2010/0047970 (2010-02-01), Eichelberger et al.
Kohl et al., “Low Cost Chip Scale Packaging and Interconnect Technology”, Proceedings of the Surface Mount International Conference, San Jose, California (Sep. 1997).
“Wire Bond and Beyond: Semiconductor Packaging Innovation”, White Paper, Freescale Semiconductor, Inc. Jul. 2006, pp. 1-9.
Leung, John, “Packaging Technology for Mobile Platforms”, Wireless and Mobile Systems Group, Freescale Semiconductor, Inc., printed from Internet on Nov. 18, 2006, pp. 1-28.
Mangrum, Marc, “Packaging Technologies for Mobile Platforms”, Wireless Mobile Systems Group, Freescale Semiconductor, Inc., Sep. 28, 2006, pp. 1-19.
“Redistributed Chip Package (RCP) Technology”, Freescale Semiconductor, Inc., printed from Internet on Nov. 18, 2006, pp. 1-6.
Keser, Beth, “Birds-of-a-Feather: Redistributed Chip Package (RCP) Broad-Range Applications for an Innovative Package Technology”, Freescale Semiconductor, Inc., Jun. 2007, pp. 1-18.
Keser, Beth, “Redistributed Chip Packaging”, http://www.semiconductor.net/index.asp? layout=articlePrint&articleID=CA6428421, Semiconductor International, Apr. 1, 2007, pp. 1-5.
Office Action for U.S. Patent Publication No. 2008/0315377 A1 (U.S. Appl. No. 12/144,725), dated Mar. 17, 2010.
Office Action for U.S. Patent Publication No. 2008/0315375 A1 (U.S. Appl. No. 12/144,720), dated Apr. 29, 2010.
Office Action for U.S. Appl. No. 12/144,840 (U.S. Patent Publication No. 2008/0315391 A1), dated Jul. 6, 2010.
Office Action for U.S. Appl. No. 12/144,720 (U.S. Patent Publication No. 2008/0315375 A1), dated Nov. 19, 2009.
Eichelberger Charles W.
Kohl James E.
Epic Technologies, Inc.
Heslin Rothenberg Farley & & Mesiti P.C.
Parker Allen L
Radigan, Esq. Kevin P.
Sefer A.
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