Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-10-01
2001-10-30
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S754090, C414S226050, C414S225010
Reexamination Certificate
active
06310486
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly an integrated automatic test system having a substantially reduced footprint for testing semiconductor devices.
BACKGROUND OF THE INVENTION
Manufacturers of semiconductor devices routinely test their products at the wafer and packaged-device levels. The testing is usually carried out by a sophisticated system commonly referred to as automatic test equipment. The equipment generally drives waveforms to and detects outputs from one or more devices-under-test (DUT). The detected outputs are then compared to expected values to determine whether the device functioned properly.
A critical concern for semiconductor manufacturers is how to maximize use of the limited floor space available for test. Typically, stringent cleanliness requirements are imposed while testing semiconductor devices to minimize the possibility of failures due to dust or debris. To meet such requirements, the automatic test equipment resides in sophisticated clean rooms that minimize the size and number of particles according to particular applications. Because of the cost necessary to operate and maintain clean rooms, maximizing clean room floor space is essential to minimizing manufacturing costs.
One type of conventional semiconductor tester generally includes a mainframe computer, or test controller, and a testhead coupled to the controller via a relatively large cable bundle. The testhead typically weighs several hundred pounds and houses a plurality of channel cards that include complex circuitry for coupling to the semiconductor devices-under-test (DUTs). The testhead is fixed to a manipulator that moves and adjusts the testhead into a variety of positions as needed.
Efficient semiconductor device testing generally requires an apparatus to move and quickly connect the device-under-test (DUT) to the tester. To move wafers, a machine called a prober is employed. To manipulate packaged-parts, a device called a handler is used. These units precisely position the semiconductor devices so that they make contact with the outputs of the tester. Probers, handlers and other devices for positioning a DUT relative to the testhead are called generically “handling apparatus.”
While the conventional tester described above appears beneficial for its intended applications, the necessity of a complex and automated manipulator to move and align the testhead in place adds undesirable expense to the tester system. Manipulators often cost upwards of a few hundred thousand dollars. Additionally, and even more importantly, the separate nature of the testhead combined with the floor space required for the manipulator adds up to a relatively large footprint. This undesirably reduces the number of testers capable of operating in a given clean room, reducing device throughput and increasing unit costs overall.
In an effort to address the tester footprint issue, one proposal for a semiconductor tester positions a mainframe/testbead unit vertically on top of a prober or handler. An example of this type of tester is found in the Teradyne Model J750 Tester, manufactured by Teradyne Inc., Boston, Mass. This construction dramatically reduces the tester footprint by making advantageous use of the vertical dimensions of the clean room. As a result, more testers are able to fit within a given horizontal clean room space.
Although the vertical configuration described above presents substantial footprint reduction benefits, the prober or handler generally supports the mainframe/testhead unit. As a result, a manipulator is still often required for servicing purposes, such as the initial installation of the unit or temporary removal of the mainframe/testhead unit from the handler or prober. Consequently, in order to plan for occasional servicing, space often must be made available in the clean room for the ingress and egress of the manipulator. The space set aside thus displaces potential floor room area for more testers and greater throughput.
What is needed and heretofore unavailable is a semiconductor test system that incorporates a minimal footprint and requires no manipulator for servicing. The integrated test cell of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The integrated test cell of the present invention provides the capability of servicing a semiconductor tester without undocking from a handling device such as a prober or handler. As a result, the use of a manipulator is unnecessary, thereby dramatically reducing costs. This also contributes to a significant reduction in the mean-time-to-repair (MTTR) parameter of the tester. Moreover, the vertical nature of the test cell presents a substantially reduced footprint, enabling the maximization of available clean room floor space.
To realize the foregoing advantages, the invention in one form comprises a semiconductor tester that is adapted for testing semiconductor devices disposed on a handling apparatus. The semiconductor tester includes a tester housing defining a self-supporting frame and formed with an externally accessible opening adapted for receiving the handling apparatus. A test controller is disposed within the housing and carried by the frame. Pin electronics including tester circuitry are responsive to the test controller and proximately coupled thereto and mounted to the frame. A docking apparatus is disposed above the opening and is adapted to couple the tester circuitry to the handling apparatus.
In another form, the invention comprises an integrated test cell for testing semiconductor devices. The integrated test cell includes a handling apparatus adapted for securing the semiconductor devices into testable positions and a tester housing defining a self-supporting frame. The frame is formed with an externally accessible opening adapted for receiving the handling apparatus. A test controller is disposed within the housing and carried by the frame. Pin electronics including tester circuitry are responsive to the test controller and proximately coupled to the test controller and mounted to the frame. A docking apparatus is disposed above the opening and is adapted to couple the tester circuitry to the handling apparatus.
In a further form, the invention comprises a cart apparatus for engaging a handling apparatus in an integrated test cell and providing selective ingress and egress of the handling apparatus to and from the test cell. The cart apparatus includes respective fore and aft channel supports disposed in parallel relationship and a pair of lateral side beams fixed to the respective ends of the fore and aft channel supports. The side beams cooperate with to channel supports to form a rectangular platform. The cart apparatus further includes a vertically upstanding handle fixed to the fore channel support and a plurality of casters disposed beneath the platform to provide selective mobility for the cart.
In yet another form, the invention comprises a method of coupling a semiconductor tester with a handling apparatus. The method includes the steps of providing an opening within the tester for receiving the handling apparatus; sliding the handling apparatus into the opening; and docking the tester to the handling apparatus.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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pate
Blagdan Isreal
Caradonna Michael A.
LeColst A. E.
Trevisan David
Trudeau Paul
Kreisman Lance
Metjahic Safet
Nguyen Jimmy
Teradyne, Inc.
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