Integrated structure layout and layout of interconnections for a

Details Integrated structure layout and layout of interconnections for a Integrated structure layout and layout of interconnections for a

1994-12-05

1996-10-15

Teska, Kevin J.

Boots, shoes, and leggings

395500, 395800, 395375, 364490, G06F 1500

Patent

active

055663850

ABSTRACT:
A semiconductor floor plan layout for integrating Data Dependency Comparator (DDC) blocks, Tag Assignment Logic (TAL) blocks, and Register Port Multiplexer (RPM) blocks to conserve valuable semiconductor real estate. The DDC blocks are arranged in rows and columns. The TAL blocks are coupled to the DDC blocks to receive dependency information. The TAL blocks are positioned in one or more of the layout regions so as to be integrated with the DDC blocks to conserve area on the integrated circuit chip. The RPM blocks are coupled to the TAL blocks to receive tag information.

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