Integrated structure layout and layout of interconnections for a

Details Integrated structure layout and layout of interconnections for a Integrated structure layout and layout of interconnections for a

1997-11-26

1998-11-03

Teska, Kevin J.

Boots, shoes, and leggings

364490, 39580025, 39580026, 39580027, 395377, 395849, 395392, 327565, G06F 1750, G06F 1700, G06F 500

Patent

active

058318712

ABSTRACT:
An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The function blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information to the tag assignment logic. The tag assignment logic provides tag information to the register file port multiplexer logic via tag output lines. The tag assignment logic is arranged on opposite sides of a center channel, so that said tag output lines are laid-out in said center channel and are fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information to a register file address port of a register file.

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