Integrated structure layout and layout of interconnections for a

Details Integrated structure layout and layout of interconnections for a Integrated structure layout and layout of interconnections for a

1996-10-11

1998-03-31

Louis-Jacques, Jacques

Boots, shoes, and leggings

364490, 395800, G06F 1500

Patent

active

057345848

ABSTRACT:
A integrated structure layout for integrating Data Dependency Comparator (DDC) blocks, Tag Assignment Logic (TAL) blocks, and Register Port Multiplexer (RPM) blocks to conserve valuable semiconductor real estate. The DDC blocks are arranged in rows and columns. The TAL blocks are coupled to the DDC blocks to receive dependency information. The TAL blocks are positioned in one or more of the layout regions so as to be integrated with the DDC blocks to conserve area on the integrated circuit chip. The RPM blocks are coupled to the TAL blocks to receive tag information.

REFERENCES:
patent: 3913074 (1975-10-01), Homberg et al.
patent: 4498134 (1985-02-01), Hansen et al.
patent: 4500963 (1985-02-01), Smith et al.
patent: 4613941 (1986-09-01), Smith et al.
patent: 4791607 (1988-12-01), Igarashi et al.
patent: 4945479 (1990-07-01), Rusterholz et al.
patent: 4964057 (1990-10-01), Yabe
patent: 5150509 (1992-09-01), Shaw et al.
patent: 5276899 (1994-01-01), Neches
patent: 5371684 (1994-12-01), Iadonato et al.
patent: 5539911 (1996-07-01), Nguyen et al.
patent: 5560032 (1996-09-01), Nguyen et al.
patent: 5560035 (1996-09-01), Garg et al.
patent: 5566385 (1996-10-01), Iadonato et al.
Luk et al., "Multistack Optimization for Data-Path Chip Layout," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, No. 1, Jan. 1991.
Mike Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1991, Jan. 1991.
John L. Hennessey et al., Computer Architecture--A Quantitative Approach, Morgan Kaufmann Publishing, Inc., San Mateo, California, 1990, Jan. 1990.

Affiliated with

Also associated with

Rating

Integrated structure layout and layout of interconnections for a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated structure layout and layout of interconnections for a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated structure layout and layout of interconnections for a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-57023