Integrated standard cell including clock lines

Details Integrated standard cell including clock lines Integrated standard cell including clock lines

1989-03-30

1991-09-03

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3073032, 307443, 307481, 357 45, H01L 2704

Patent

active

050457250

ABSTRACT:
An integrated standard cell consisting of a plurality of standard cells each having a logical area, at least one power supply line, and one ground line, which further includes two clock signal lines for supplying clock signals. These signals are formed within each standard cell and are provided outside of the power supply line and the ground line, in parallel thereto. The two clock signal lines are connected to the logical area through each shunt line which substantially extends in the vertical direction to the clock signal lines. With this construction, a quantitative prediction for the time delay of clock signals which propagate in the clock signal lines becomes easy, thereby preventing any skew of the clock signals from occurring.

REFERENCES:
patent: 4742383 (1988-05-01), Fitzgerald
patent: 4750026 (1988-06-01), Kuminobu et al.
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4825107 (1989-04-01), Naganuma et al.
patent: 4851717 (1989-07-01), Yabe
Bala Subramanian et al., "Program Logic Array with Metal Level Personalization", IBM T. D. B., vol. 19, No. 6, Nov. 1976, pp. 2144-2145.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., 1980, Plate 11 and pp. 150-154.

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