Integrated solution to high voltage load dump conditions

Details Integrated solution to high voltage load dump conditions Integrated solution to high voltage load dump conditions

1991-06-28

1993-08-10

DeBoer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361 91, 257356, H02H 904

Patent

active

052354890

ABSTRACT:
A structure for protecting an integrated circuit against high supply line voltages is formed in an epitaxial silicon layer of one conductivity type on a semiconductor substrate of another conductivity type. A transistor is formed in the epitaxial layer to protect the integrated circuit against low range overvoltages. A highly doped region in the epitaxial layer on one side of the transistor of the same conductivity type as the expitaxial layer extends to the substrate. The highly doped region is connected to a reference potential and establishes a parasitic SCR with the transistor and substrate with a controllable breakover voltage above the protection voltage of the transistor.

REFERENCES:
patent: 4578695 (1986-03-01), Delaporte et al.
patent: 4775912 (1988-10-01), Menniti et al.
patent: 4896243 (1990-01-01), Chatterjee et al.
patent: 4949212 (1990-08-01), Lenz et al.
patent: 5032742 (1991-07-01), Zandera

Affiliated with

Also associated with

Rating

Integrated solution to high voltage load dump conditions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated solution to high voltage load dump conditions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated solution to high voltage load dump conditions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1730266