Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
2000-01-04
2004-03-30
Tran, Khai (Department: 2731)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
Reexamination Certificate
active
06714606
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory buffers generally and, more particularly, to an integrated services digital broadcasting (ISDB) de-interleaver architecture.
BACKGROUND OF THE INVENTION
The Japanese integrated services digital broadcasting (ISDB) standard uses a 203×8 block interleaver before a convolution encoder and after an RS encoder and randomizer. Data bytes are transmitted in the format of 203 bytes/slot, 48 slots/frame, 8 frames/ super frame. The interleaver operates on the n-th slot of every frame in one super frame, where n=0, 1, 2, . . . , 47. Upon receipt, the data bytes must be de-interleaved.
Referring to
FIG. 1
, a block diagram of a conventional block de-interleaver
10
is shown. The block de-interleaver
10
is used to de-interleave super frames in the Japanese integrated services digital broadcasting (ISDB) standard. The block de-interleaver
10
requires two super frame memories
12
and
14
to de-interleave a received signal. The block de-interleaver
10
writes data from the received signal into one super frame memory
12
while presenting data of a previously received signal from the other super frame memory
14
. When one super frame of data is finished, the reading and writing exchange memory frames.
In the example of the Japanese ISDB standard, the super frame memory size is 76.125K bytes. The need for two super frame memories doubles the memory used to implement the device. Doubling the memory on a chip increases the cost and decreases the chip yield. A solution is needed that will use less memory to de-interleaved a super frame.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory, a write pointer, a read pointer and a control circuit. The memory may have a plurality of memory locations accessed by a plurality of addresses. The write pointer may be configured to write data to the memory in response to a sequence of write addresses generated in response to a first control signal. The read pointer may be configured to read data from the memory in response to a sequence of read addresses generated in response to a second control signal. The control circuit may be configured to generate (i) the first control signal, and (ii) the second control signal. The order data is read from said memory may comprise a de-interleaved pattern with respect to the order the data is written to the memory.
The objects, features and advantages of the present invention include providing an integrated services digital broadcasting de-interleaver architecture with slightly more than one super frame of memory that may de-interleave a Japanese ISDB standard super frame at a lower cost and/or higher chip yield.
REFERENCES:
patent: 5822008 (1998-10-01), Inoue et al.
patent: 6353900 (2002-03-01), Sindhushayana et al.
patent: 6480976 (2002-11-01), Pan et al.
Mogre Advait
Qian Cheng
LSI Logic Corporation
Maiorana PC Christopher P.
Tran Khai
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