Integrated semiconductor structure with incorporated alignment m

Details Integrated semiconductor structure with incorporated alignment m Integrated semiconductor structure with incorporated alignment m

1991-01-14

1991-09-24

Carroll, J.

357 51, 357 55, H01L 2702, H01L 2906

Patent

active

050518070

ABSTRACT:
A semiconductor integrated circuit structure formed on a substrate and composed of a plurality of groups of integrated circuit chips each in the form of an elongated strip having a short dimension and a long dimension which is markedly longer than the short dimension, with adjacent chips in each group being spaced from one another by linear regions including a plurality of first linear regions extending parallel to the long dimension of the chips and at least one second linear region extending parallel to the short dimension of the chips, wherein, in each group, the at least one second linear region has a width greater than at least one of the first linear regions.

REFERENCES:
patent: 3883437 (1975-05-01), Nummedal et al.
patent: 4618262 (1986-10-01), Maydan et al.
patent: 4755750 (1988-07-01), Leuschner
patent: 4823012 (1989-04-01), Kosugi
"Hybrid Alignment: 5:1 Stepper with 1:1 Scanner", Fumiaki Ushiyama, Semiconductor International, Apr. 1985, pp. 180-183.
"Hybrid lithography . . . " Jerris H. Peavey, et al, SPIE Proceeding, vol. 334, 1982, pp. 149-156.

Affiliated with

Also associated with

Rating

Integrated semiconductor structure with incorporated alignment m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated semiconductor structure with incorporated alignment m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated semiconductor structure with incorporated alignment m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1700641