Integrated semiconductor structure with combined dielectric and

Details Integrated semiconductor structure with combined dielectric and Integrated semiconductor structure with combined dielectric and

1975-07-18

1977-05-31

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148175, H01L 2120

Patent

active

040267369

ABSTRACT:
This disclosure is directed to an integrated semiconductor structure with combined dielectric and PN junction isolation including the fabrication method therefor wherein a compensating P type channel is formed adjacent to the dielectric side isolation across one end portion of the electrically isolated N type collector region as well as around the bottom portion of the dielectric side isolation material or layer in order to overcome the N channel inversion (in P type semiconductor material) that is formed when the dielectric isolation material is silicon dioxide. The disclosed structure is an NPN transistor device having a buried sub-collector region of N+ type conductivity and further includes a P type substrate thereby providing a PN junction isolating substrate. The silicon dioxide material or layer is used to electrically isolate the side portions of the NPN transistor device from adjacent devices. The side dielectric isolation region is formed in a substantially V-shaped configuration with polycrystalline silicon forming the material located within the dielectric V-shaped member thereby providing a substantially planar surface for the integrated semiconductor structure.

REFERENCES:
patent: 3769562 (1973-10-01), Bean
patent: 3783044 (1974-01-01), Cheskis et al.
patent: 3798753 (1974-03-01), Camenzind et al.
patent: 3878552 (1975-04-01), Rodgers
patent: 3913124 (1975-10-01), Roberson

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