Static information storage and retrieval – Powering
Reexamination Certificate
2000-02-22
2001-05-22
Mai, Son (Department: 2818)
Static information storage and retrieval
Powering
C365S051000, C365S063000
Reexamination Certificate
active
06236612
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the field of semiconductor technology. More specifically, the present invention relates to an integrated semiconductor memory configuration with a plurality of memory cell fields. A respective one of the memory cell fields can be activated at a given time as defined. The configuration further includes a voltage generator for delivering a supply potential to the memory cell fields, first electrical supply lines between the voltage generator and the plurality of memory cell fields, and second electrical supply lines between the plurality of memory cell fields.
To date, individual memory cell fields in integrated semiconductor memory configurations have each been connected with low resistance to a voltage generator via electrical supply lines in order to provide the individual memory cell fields with the supply voltage that is necessary in each case. Now, the individual memory cell fields in an integrated semiconductor memory configuration are activated successively as defined, so that, at a given instant, an accurately defined power quantity must be provided for a memory cell field which is currently activated.
The currently activated memory cell field thus forms an active region, while all the other memory cell fields represent inactive regions at the time that the activated memory cell field is activated.
Experiments have shown that it is sufficient to transfer a capacitance of approximately 70 pF in order to activate a memory cell field. A typical semiconductor memory configuration with a multiplicity of memory cell fields has a capacitance of approximately 2 nF available.
SUMMARY OF THE INVENTION
The object of the invention is to provide an integrated semiconductor memory configuration which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which, while being of simple design, is immediately able to provide the power required to activate a memory cell field using short supply lines.
With the above and other objects in view there is provided, in accordance with the invention, an integrated semiconductor memory configuration, comprising:
a plurality of memory cell fields each being respectively activatable at a given time;
a voltage generator for delivering a supply potential to the memory cell fields;
first electrical supply lines connected between the voltage generator and the plurality of memory cell fields; and
second electrical supply lines connected between the plurality of memory cell fields;
the first electrical supply lines having a relatively high resistance and the second supply lines having a relatively low resistance.
In other words, the objects of the invention are satisfied in the integrated semiconductor memory configuration of the type mentioned in the introduction wherein the first supply lines are designed to have a high resistance and the second supply lines are designed to have a low resistance.
In doing so, the invention takes a path which is completely different from that of the prior art: instead of designing the supply lines between the voltage generator and the individual memory cell fields to have a low resistance in order to ensure that the power required in each case is thus provided quickly, the connection between the voltage generator and the individual memory cell fields is designed to have a high resistance in the integrated semiconductor memory configuration according to the invention. Accordingly, the supply lines between the individual memory cell fields have a low resistance. In this manner, the total capacitance of all the memory cell fields which are currently not activated is advantageously utilized so that a particular memory cell field can be activated at a given instant.
This means that the wiring complexity can be minimized without impairing the electrical parameters as a result of dips in the supply voltage. “Self-buffering” of a selected memory cell field from all the other memory cell fields, which are not activated at this instant, is particularly advantageous because precisely predictable, defined activation is achieved in each case. The power required to activate a particular memory cell field is defined and is the same for the individual memory cell fields. This power is derived from the capacitors on the memory cell fields which are currently not activated. The memory cell fields as a whole are connected via a high-resistance supply line to the voltage generator, which thus continuously “refreshes” the power stored in the capacitors in the individual memory cell fields.
In accordance with an added feature of the invention, the memory cell fields are disposed in a row, and the second supply lines are routed along the two sides of the row of memory cell fields.
In accordance with another feature of the invention, the second supply lines surround the memory cell fields.
In other words, the low-resistance supply lines are routed along both sides of the row of memory cell fields, whereas the latter have previously been wired together only on one side using a high-resistance connection line. In addition, these low-resistance supply lines are also arranged around the individual memory cell fields, so that each individual memory cell field is “framed” by the low-resistance supply lines.
In accordance with an additional feature of the invention, an additional second supply line (also a low-resistance supply line) is routed in the center of the memory cell fields.
In accordance with a further feature of the invention, the second supply lines are formed with a track width of between approximately 3 and 4 &mgr;m.
In accordance with a concomitant feature of the invention, the first and second supply lines are made of aluminum and/or copper.
Hence, the essential feature of the present invention is the connection of the individual memory cell fields to one another by means of low-resistance supply lines and the connection of these memory cell fields to a voltage generator using a high-resistance supply line. In addition, the low-resistance supply lines are designed to go around the individual memory cell fields, thus ensuring that the latter are supplied at low resistance. If a particular memory cell field is activated, the power required for this is derived from the other memory cell fields, which are inactive at this instant. The power consumed is continuously refreshed via the high-resistance supply line between the memory cell fields and the voltage generator.
Thus, the integrated semiconductor memory configuration according to the invention uses a multiplicity of memory cell fields, representing extensive circuit regions, to buffer the supply potentials of the few, simultaneously activated regions in the form of a respectively driven memory cell field. In this case, these circuit regions are connected by the low-resistance supply lines, which represent a “power network”, this network being coupled to a voltage generator using a high-resistance supply line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor memory configuration with self-buffering of supply voltages, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4901284 (1990-02-01), Ochii et al.
patent: 5293559 (1994-03-01), Kim et al.
patent: 5321646 (1994-06-01), Tomishima et al.
patent: 5867440 (1999-02-01), Hidaka
Chrysostomides Athanasia
Feurle Robert
Kaiser Robert
Schneider Helmut
Greenberg Laurence A.
Lerner Herbert L.
Mai Son
Siemens Aktiengesellschaft
Stemer Werner H.
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