Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
1997-12-30
2002-03-05
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S112000, C327S333000
Reexamination Certificate
active
06353353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including a circuit which performs high-speed and/or large-current switching, such as a driver circuit or the like.
2. Description of the Related Art
FIG. 1
illustrates a driving circuit which uses a CMOS (complementary metal oxide semiconductor) inverter. In
FIG. 1
, a control circuit
101
outputs a control signal
104
to a predriver
107
based on a signal from the outside or a signal within an IC (integrated circuit) including the driving circuit. The predriver
107
is an inverter comprising a pMOS transistor M
101
and an nMOS transistor M
102
. The predriver
107
inverts the output
104
of the control circuit
101
, and drives gates of a driver
108
at the final stage comprising a pMOS transistor M
103
and an nMOS transistor M
104
. The pMOS transistor M
103
and the nMOS transistor M
104
constituting the driver
108
are large enough to charge/discharge a load capacitance C
101
at a desired speed. There are also shown a positive power-supply line
102
, a GND (ground) line
103
, and an output
106
. An output
105
of the predriver
107
is inverted by the driver
108
to provide the output
106
. The load capacitance C
101
may be the capacitance of a gate within the IC, or a load at the outside of the IC.
In Japanese Patent Laid-Open Application (Kokai) No. 5-235275 (1993), a method is proposed in which, in order to suppress noise from a power supply, a bypass capacitance is provided between power supply lines, and a thin-film resistor is connected in series in order to prevent destruction of the capacitance. This method will be described with reference to FIGS.
2
(A) and
2
(B). FIG.
2
(A) is a schematic plan view, and FIG.
2
(B) is a schematic cross-sectional view taken along line
2
B—
2
B shown in FIG.
2
(A).
In FIGS.
2
(A) and
2
(B), reference numeral
11
represents a silicon substrate as the one used in an ordinary silicon integrated circuit. A first field insulating layer
12
(about 500 nm thick) is formed using silicon oxide. A first conductive layer
13
(about 500 nm thick) is formed using aluminum. However, any other appropriate metal, polysilicon or the like may also be used for forming the first conductive layer
13
. The first conductive layer
13
serves as a lower electrode of a capacitor, and an extended portion of the first conductive layer
13
operates as one of a set of power-supply lines (for example, a ground line). A dielectric layer.
14
(about 50 nm thick) is formed using silicon nitride. A second field insulating layer
15
(about 500 nm thick) is formed using silicon oxide. A thin-film resistive layer
16
(about 10 nm thick) is formed using a thin-film SiCr-type or NiCr-type resistive material. The resistance value of this thin-film resistive layer
16
is about 1-2 k&OHgr;. A third field insulating layer
17
(about 150 nm thick) is formed using silicon oxide. There are also shown openings for contact
18
a
and
18
b
. A second conductive layer
19
a
and a third conductive layer
19
b
(both about 1,000 nm thick) are formed using aluminum. However, any other appropriate metal, polysilicon or the like may also be used for forming these conductive layers. The second conductive layer
19
a
serves as an upper electrode of the capacitor, and an extended portion of the second conductive layer
19
a
is connected to one end of the thin-film resistive layer
16
. The third conductive layer
19
b
is connected to the other end of the thin-film resistive layer
16
, and an extended portion of the third conductive layer
19
b
operates as the other line of the power-supply lines (for example, a plus power-supply line).
As is apparent from the foregoing description, the first conductive layer
13
, the dielectric layer
14
and the second conductive layer
19
a
at the opening
18
a
constitute a capacitor, which operates as a bypass capacitor. The capacitor and the thin-film resistive layer
16
constitute a series circuit, which is provided between the two power-supply lines (for example, between the ground line and the plus power-supply line) of the integrated circuit.
As described above, in the case shown in FIGS.
2
(A) and
2
(B), by providing the series circuit of the capacitance and the thin-film resistor between the power-supply lines of the integrated circuit, destruction of the coupling capacitance is prevented.
When using the driving circuit shown in
FIG. 1
by forming it on a semiconductor substrate and encapsulating the IC in a package, a finite parasitic inductance is present in the package and bonding wires. Hence, when intending to perform high-speed and/or large-current switching, voltages in the power-supply line and the ground line within the IC change to apply a voltage exceeding the power-supply voltage to the transistor at the output stage, thereby, in some cases, degrading the reliability of the IC. In general, as the degree of integration of a device increases, the breakdown voltage decreases. Accordingly, when using a driving circuit as shown in
FIG. 1
, it is necessary to use a device of a lower degree of integration having an allowance in the breakdown voltage, thereby providing, in some cases, a disadvantage from the viewpoint of improvement in the performance and in the degree of integration.
Such a problem will now be described with reference to FIG.
3
. The configuration shown in
FIG. 3
is obtained by adding parasitic inductances L
101
and L
102
and parasitic resistances R
101
and R
102
caused by the package and bonding wires to the configuration shown in FIG.
1
. In
FIG. 3
, the same components or signals as those shown in
FIG. 1
are indicated by the same reference numerals, and further description thereof will be omitted.
In
FIG. 3
, a power-supply input terminal
114
provides the integrated circuit with a positive power supply. A power-supply input terminal
115
is connected to the ground. A positive power-supply interconnection
116
is formed on the semiconductor substrate. A ground interconnection
117
is also formed on the semiconductor substrate. A package (PKG)
118
encapsulates the integrated circuit. Changes in the power-supply lines
116
and
117
when the output
105
of the predriver changes will now be described. In a usually used package, such as a QFP (quad flat package) or the like, a parasitic inductance of about 10 nH, and a parasitic resistance of the order of 0.1 &OHgr; are present. Accordingly, when switching a current of 500 mA in 2 nsec, the electromotive force generated in the parasitic inductance is estimated to be:
V=L(di/dt)=10 nH×500 mA/2 nsec=2.5 V.
This variation is not neglible when a power-supply voltage of about 5-10 V is used. Actually, since a greater change occurs in current at the moment of switching, a larger variation occurs in the power-supply lines. Furthermore, since variations occur in both of the positive power-supply line and the ground line, a larger voltage is applied to the device at the output stage.
FIGS.
4
(A) through
4
(D) illustrate variations in time in the input voltage of the driver, the power-supply voltages, and the source-drain voltages of the MOS transistors at the output stage.
FIG.
4
(A) is a diagram illustrating the waveform of the input voltage of the driver
108
. FIG.
4
(B) is a diagram illustrating the waveforms of voltages in the power-supply line and the ground line. FIGS.
4
(C) and
4
(D) illustrate the source-drain voltages of the pMOS transistor M
103
and the nMOS transistor M
104
, respectively. When the input voltage rises at a time T
1
shown in FIG.
4
(A), the nMOS transistor M
104
is gradually turned on, so that a current flows through the driver
108
and a current as a result of discharging electric charges stored in the load C
101
flows through the nMOS transistor M
104
. At that time, voltage drops occur in the parasitic elements L
101
, R
101
, L
102
and R
102
shown in
FIG. 3
Callahan Timothy P.
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Nguyen Hai L.
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