Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-05-15
2004-11-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S226000, C365S063000
Reexamination Certificate
active
06816432
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor circuit having at least two transistors, which are both operated with a first operating voltage and which each have a control electrode and a layer of a dielectric adjacent to the respective control electrode. The first and second transistors are connected up in such a way that the first and second transistors are switched with different frequencies on average over time. An average switching frequency of the second transistor is less than an average switching frequency of the first transistor.
Such semiconductor circuits have been customary for decades in semiconductor technology and are predominantly produced from MOSFETs in CMOS technology i.e. as a combination of n-channel transistors and p-channel transistors. It is usual for the source and drain of the transistors to be implanted into the semiconductor substrate after the prior patterning, in their center, of a dielectric, usually made of an oxidic material such as silicon dioxide, with the overlying gate contact.
Depending on the application purpose, vertical transistors with a source-drain channel running perpendicularly to the substrate surface are also produced. Moreover, there are further conceivable configurations of transistors that likewise have a control electrode that, in a similar manner to the gate electrode of a MOSFET, is isolated from the further electrodes of the transistor by a dielectric.
In MOSFETs, the electric field strength penetrating through the dielectric controls the formation of a channel between the remaining transistor electrodes. A switching operation alters the voltage between the gate and the source and, depending on the type of MOSFET, effects or prevents the formation of a channel beneath the dielectric.
In order to enable the channel formation to be controlled as directly and controllably as possible, the dielectric, which is usually a limited aereal region of a layer deposited on the semiconductor substrate is made as thin as possible. The layer thickness of the dielectric, typically being a few nanometers, is significantly less than the layer thickness of the overlying gate layers, but must be large enough to prevent tunneling through the dielectric on account of the fields present. Proceeding from this necessity, the layer thickness of the dielectric is always chosen to be as small as possible, in order to control the transistor optimally.
What are of particular importance for the electrical switching behavior of the transistor are its short-channel behavior and its transistor performance. A decreasing gate length is accompanied by a decrease in the saturation current that can be achieved between source and drain. It is nevertheless necessary, despite the advancing miniaturization of the transistors, to ensure a sufficiently high saturation current. This is all the more important the smaller the dimensioning of the gate length. At the present time, reliable transistors having gate lengths of less than 150 nm are produced.
Also of importance is the threshold voltage, at which the MOSFET switches, i.e. at which the formation or the collapse of the channel between the source and drain commences. The lower the threshold voltage, the more easily the transistor can be controlled.
For these reasons, for decades the layer thickness of the dielectric of the transistors has been made as small as possible and approximated as far as possible to the minimum layer thickness at which, depending on the semiconductor generation, reliable operation of the transistors is still possible.
More complex circuits often have regions in which transistors are supplied with different operating voltages. Roughly, a distinction can be made between low-voltage transistors having an operating voltage of between 1 and 5 V, high-voltage transistors having an operating voltage of between 10 and 20 V and power transistors having an operating voltage of above 40 V. The different supply voltages require the transistors to have dimensions of different magnitudes. However, transistors are dimensioned in different sizes also in the case of significantly smaller voltage differences within a single region, for instance in that of the low-voltage transistors. It is known, for instance, in the case of transistors operated with different supply voltages, to configure the layer thickness of the respective dielectric with different magnitudes in order to achieve a lifetime that is approximately of the same length for both transistors. Thus, differences between the operating voltages of a few volts typically lead to layer thickness differences of the order of magnitude of a few nanometers.
This measure has long resulted in an approximately identical reliability of different transistors in regions of different supply voltages within an integrated semiconductor circuit.
Furthermore, there continue to exist integrated semiconductor circuits whose transistors are configured for a uniform operating voltage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit having transistors that are switched with different frequencies that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the reliability and the controllability of such semiconductor circuits are improved. In particular, the object of the invention is, with the lifetime of an integrated circuit remaining the same, to further improve its controllability at least in partial regions or, with no reduction in the controllability, to affect an overall increase in the lifetime of the circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit. The integrated semiconductor circuit contains two transistors, including a first transistor and a second transistor, operated with an operating voltage. The two transistors are connected up such that the transistors are switched with different frequencies on average over time, the second transistor having an average switching frequency less than an average switching frequency of the first transistor.
The first transistor has a first control electrode and a first dielectric layer disposed adjacent to the first control electrode, and the second transistor has a second control electrode and a second dielectric layer disposed adjacent to the second control electrode. The second dielectric layer has a given thickness that is less than a given thickness of the first dielectric layer.
The object is achieved according to the invention by virtue of the fact that the layer thickness of the dielectric of the second, less frequently switched transistor, i.e. of the second dielectric, is less than the layer thickness of the dielectric of the first, more frequently switched transistor, i.e. of the first dielectric.
The present invention exploits the fact that different transistors of a semiconductor circuit are addressed with different frequencies. The frequency with which a transistor is switched back and forth between its on state and its off state varies depending on the function and configuration of the transistor within the semiconductor circuit.
Semiconductor circuits are usually clocked with a predetermined frequency, so that a check and, if appropriate, a change of the switching states takes place at discrete, very short time intervals. Considered over many clock periods, it is possible to specify a probability value for the probability with which a specific transistor is switched per clock cycle. The switching probability or switching frequency is inversely proportional to the average temporal duration of a switching state of this transistor, i.e. to the average time interval between successive switching times. The latter differs depending on the transistor and may vary by several powers of 10 between transistors of different regions of the semiconductor circuit.
The invention exploits the fact that the probability of tunneling through the dielectric is reduced
Feurle Robert
Savignac Dominique
Greenberg Laurence A.
Locher Ralph E.
Phan Trong
Stemer Werner H.
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