Electrical transmission or interconnection systems – Switching systems – Condition responsive
Reexamination Certificate
1998-11-20
2002-09-03
Fleming, Fritz (Department: 2836)
Electrical transmission or interconnection systems
Switching systems
Condition responsive
C327S530000
Reexamination Certificate
active
06445091
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated semiconductor circuit having at least two supply networks that are supplied independently of one another. The two supply networks include a first, load supply network, which is associated with a load circuit, and a second, driver supply network, which is associated with a driver circuit. Each supply network has a ground path with ground lines and a supply path with supply potential lines separate from the ground path.
Increasingly high clock frequencies in digital semiconductor chips, such as DRAM storage chips, impose ever shorter switching times on the output drivers provided in the semiconductor chip. These very short switching times are the cause of current surges during the switching time, which in turn cause voltage fluctuations in the supply networks of the semiconductor chip, and hence noise which can adversely affect the correct operation of the digital circuits produced on the semiconductor chip. In order to remedy these weaknesses, attempts have been made to develop the digital circuits such that they are as less sensitive to the effects of noise, but it has not been possible to achieve this without a loss of speed. In addition, an attempt was made to provide separate supply pins for supplying the output driver circuits (OCD =off chip driver), but this requires a separate voltage supply and hence increased circuitry.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit having at least two supply networks which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the noise caused by current surges during switching of the driver circuits is considerably reduced in the integrated semiconductor circuit, even without a loss of speed.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit, including: at least two supply networks supplied independently of one another including a load supply network associated with a load circuit and a driver supply network associated with a driver circuit, the at least two supply networks including ground paths and supply paths and each of the at least two supply networks has a ground path with ground lines and a supply path with supply potential lines separate from the ground path; and a compensating circuit alternatively coupling at least one of the ground paths and the supply paths of the at least two supply networks to one another.
According to the principle of the invention, a compensating circuit is provided which alternatively couples the ground paths and/or the supply paths of the at least two supply networks to one another. Expediently, the compensating circuit has a logic circuit which detects the load on one of the at least two supply networks in the form of a predetermined logic value (logic ONE or logic ZERO) and, in response to this, controls the coupling element. The coupling element is likewise provided in the compensating circuit, so as to make an electrical connection between the ground paths and/or the supply paths of the at least two supply networks.
If the load circuit disposed on the semiconductor chip reads a logic ONE, then, in this case, the positive supply potential of the driver circuits is loaded. If a logic ZERO is read, then the ground potential of the driver circuits is loaded. Hence, in the semiconductor circuit according to the invention, the ground potential of the load supply network (ground potential of the actual logic circuits) is connected, while a logic ONE is being read, to the ground potential of the driver supply network (ground potential of the driver circuits), and is thus stabilized. Accordingly, when a logic ZERO is being read, the positive supply potential of the load supply network is connected to the positive supply potential of the driver supply network. By alternatively connecting the different supply lines in this way, the noise on the supply lines for the load circuits can be considerably reduced.
In accordance with an added feature of the invention, the supply paths of the at least two supply networks supply the same potential when in operation, and the ground paths of the at least two supply networks have the same potential when in operation.
In an embodiment of the invention that is preferred in terms of circuitry, the coupling element is a switching transistor that is monolithically integrated in the semiconductor circuit.
The inventive semiconductor circuit with the compensating circuit is particularly suitable for digital semiconductor circuits with high clock frequencies, for example digital DRAM memory components or SDRAM semiconductor components.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor circuit having at least two supply networks, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4978905 (1990-12-01), Hoff et al.
patent: 5059822 (1991-10-01), Dukes
patent: 5319260 (1994-06-01), Wanlass
patent: 5332932 (1994-07-01), Runaldue
patent: 5438277 (1995-08-01), Sharpe-Geisler
patent: 6219294 (2001-04-01), Huber et al.
patent: 19700988 (1997-07-01), None
patent: 0545359 (1993-06-01), None
Fleming Fritz
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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