Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – Specified materials
Reexamination Certificate
2002-01-25
2004-09-14
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
Specified materials
C257S471000, C257S485000, C257S280000, C257S288000
Reexamination Certificate
active
06791154
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2001-27128 filed on Feb. 2, 2001, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated semiconductor circuit device, a process of manufacturing the same, an IC module and an IC card.
2. Description of Related Art
A non-contact IC card is provided with an electricity receiving coil and a diode bridge circuit, which allow supply of a power source voltage and transfer of control signals and data between the IC card and a so-called reader/writer without any contact therebetween. In general, the diode bridge circuit used herein is formed of a Schottky barrier diode showing a small forward rise voltage such that a response speed increases.
Japanese Unexamined Patent Publication No. Sho 63 (1988)-185693 discloses an example of the diode bridge circuit.
FIG. 5
shows a schematic plane view of the integrated semiconductor circuit device. In
FIG. 5
, there shown are an N-channel MOSFET
100
, a P-channel MOSFET
110
, an N-type well power source
120
and a Schottky barrier diode
130
which are formed on a P-type silicon substrate.
FIG. 6
is a schematic section taken along the line III—III in FIG.
5
.
On the P-type silicon substrate
51
, an N-type well (semiconductor region)
52
and a P-type channel stopper
53
are formed. Thin gate oxide films
54
(regions
54
′ for forming transistors) and thick field oxide films
55
are formed on the silicon substrate
51
by a common selective oxidation technique, i.e., so-called LOCOS.
Then, gate electrodes
56
of polysilicon are formed on the gate oxide films
54
. Using the gate electrodes
56
and the thick field oxide films
55
as a mask, arsenic ions are injected to form source/drain regions
57
of the N-channel MOSFET
100
on the silicon substrate
51
and a well power source
120
in the N-type well
52
.
For increasing a breakdown voltage of the Schottky barrier diode against a backward voltage, boron ions are injected to form low concentration P
−
diffusion layers
58
in the N-type well
52
. Boron ions are injected again to form source/drain regions
59
of the P-channel MOSFET
110
in the N-type well
52
and P
+
diffusion layers
59
′ for the Schottky barrier diode in the P
−
diffusion layers
58
.
An interlayer insulating film
60
is then deposited on. the entire surface, in which contact holes
61
are formed at desired positions. The contact holes
61
are buried with metal wires
62
made of a thin film of aluminum (Al) or the like, which are subjected to a thermal treatment to form the N-channel MOSFET
100
and the P-channel MOSFET
110
, as well as the Schottky barrier diode
130
between the metal wires
62
and the N-type well
52
.
However, as the integrated semiconductor circuits of miniaturized design are intended, the electrical connection between the source/drain regions of the MOSFET is established by a technique different from a conventional one and for example, a so-called plug structure using tungsten (W) or the like is required. Further, a silicide layer such as a titanium silicide layer is formed on the surfaces of the source/drain regions and the gate electrodes of the transistor, respectively, for reducing a wiring resistance.
In order to achieve a diode bridge circuit formed of the Schottky barrier diode and a periphery circuit formed of a MOSFET on a single silicon substrate by a process used in accordance with the miniaturization of the integrated semiconductor circuits, i.e., a process of forming a wiring structure different from the conventional one, the Schottky barrier needs to be formed separately from the formation of the wires for the MOSFET.
In other words, the step of forming openings in regions of anode/cathode electrodes of the Schottky barrier diode and the step of depositing metal for forming the Schottky barrier are added, which causes complication and increases costs. For forming the Schottky barrier diode without increasing the steps, required is the Schottky barrier diode having the same structure as that of a contact region of the MOSFET
SUMMARY OF THE INVENTION
According to the present invention, provided is an integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.
The present invention further provides a process of manufacturing an integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, the process comprising the steps of: exposing surfaces at desired positions in source/drain regions and a gate electrode of the MOS transistor, as well as in a region for forming a Schottky barrier of the Schottky barrier diode; converting the exposed surfaces to amorphous; forming metal layers capable of reacting to be silicide on the exposed surfaces; subjecting the exposed surfaces and the metal layers to a thermal treatment for silicidation to form silicide layers; and conducting a thermal treatment for reducing a resistance of the silicide layers.
According to the present invention, there is provided an IC module including the above-described integrated semiconductor circuit device.
Still according to the present invention, there is provided an IC card including the above-described IC module.
In summary, the present invention has been achieved to solve the above-mentioned problem. The silicide layers are formed at the desired positions of the source/drain regions and the gate electrodes of the MOSFET as well as of the region for forming the Schottky barrier.
According to the present invention, the Schottky barrier made of the silicide layer is formed simultaneously with the silicide layers formed in self-alignment at the desired positions of the source/drain regions and the gate electrodes of the MOSFET, and both of the silicide layers are connected to the wiring layers via the contact plugs. Accordingly, the transistor and the Schottky barrier diode are formed to have similar structures. Therefore, the step of forming the openings for forming the Schottky barriers after the formation of the plugs in the transistor and the step of patterning the electrodes can be omitted. Further, a high integration is achieved because the barriers are formed in self-alignment. Moreover, occurrence of spikes, which have been generated when the Schottky junction is established between metal and silicon, is inhibited, because the Schottky junction is established between the silicide layer and silicon substrate. Thus, increase in product yield is expected.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
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patent: 5225359 (1993-07-01), DeLong
patent: 5323053 (1994-06-01), Luryi et al.
patent: 5731691 (1998-03-01), Noto
patent: 5956137 (1999-09-01), Lim et al.
patent: 6122494 (2000-09-01), Tuttle
patent: 6255704 (2001-07-01), Iwata et al.
patent: 2001/0005610 (2001-06-01), Fukase et al.
patent: 0 580 242 (1994-01-01), None
patent: 0 702 316 (1996-03-01), None
patent: 0 831 415 (1998-03-01), None
patent: 0 902 476 (1999-03-01), None
patent: 63-185693 (1988-08-01), None
patent: WO 00/7
Matsumoto Hironori
Ohmi Toshinori
Birch & Stewart Kolasch & Birch, LLP
Flynn Nathan J.
Greene Pershelle
Sharp Kabushiki Kaisha
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