Integrated semiconductor circuit device

Details Integrated semiconductor circuit device Integrated semiconductor circuit device

1985-11-18

1988-05-24

James, Andrew J.

357 71, H01L 2348, H01L 2952

Patent

active

047469650

ABSTRACT:
Disclosed is an integrated semiconductor circuit device which has a plurality of cell arrays formed in parallel on a surface region of the substrate, and a three-layer wire formed on the substrate and between each cell array. The direction of a wire track of a second layer wire is originally determined in a direction parallel to the cell arrays, and the direction of wire tracks of first and third layer wires is originally determined in a direction orthogonal to the originally determined direction of the wire track of the second layer wire. The first layer wire and the third layer wire are formed on the same wire track. Part of the third layer wire is formed on a wire track orthogonal to the originally determined direction of the wire track of the third layer, and the third layer wire and the second layer wire are connected to each other on the wire track which is orthogonal to the originally determined direction of the wire track of the third layer wire.

REFERENCES:
patent: 4197555 (1980-04-01), Uehara et al.
patent: 4513307 (1985-04-01), Brown
patent: 4656732 (1987-04-01), Teng et al.
"Three-Layer Channel Routing", IEEE Trans. Computer Aided Des, vol. CAD-3, pp. 156-163, Y. K. Chen and M. L. Liu, Apr. 1984.
IBM Technical Disclosure Bulletin, vol. 26, No. 6, Nov. 1983, pp. 2842-2845, New York, US; L. B. Caldwell et al: "Optimum Wiring Connections for Single-Metal Level Integrated Circuits".
Saigo, T., Niwa, K., Ohto, T., Kurosawa, S., and Takada, T., "A Triple-Level Wired 24K-Gate CMOS Gate Array", The Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 1005-1010.

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