Metal treatment – Stock – Ferrous
Patent
1979-10-17
1982-04-06
Larkins, William D.
Metal treatment
Stock
Ferrous
148175, 357 36, 357 46, 357 50, 357 52, 365179, H01L 2704, H01C 700
Patent
active
043239137
ABSTRACT:
An integrated semiconductor circuit arrangement is provided which comprises a substrate of semiconductor material of one conductivity type, an epitaxial layer of the opposite conductivity type formed on one major surface of the substrate, the epitaxial layer having function elements such as transistors, diodes, resistances, and so forth, formed therein. A least some of these function elements are located in insulated regions provided for them which in the boundary area between the substrate and the epitaxial layer are bounded by a pn junction and which at right angles to this boundary area are bounded by oxide walls which extend through the epitaxial layer to the substrate. The oxide walls are surrounded by a resistor region of the said one conductivity type which extends through the epitaxial layer to the substrate.
REFERENCES:
patent: 3631311 (1971-12-01), Engbert
patent: 3648125 (1972-03-01), Peltzer
patent: 3911471 (1975-10-01), Kooi et al.
patent: 3961356 (1976-06-01), Kooi
patent: 3962717 (1976-06-01), O'Brien
Wiedmann, IBM Tech. Discl. Bulletin, vol. 13, No. 9, Feb. 1971, p. 2469, (357-51).
Evans et al, IEEE J. of Solid-State Circuits, vol. SC 8, No. 5, Oct. 1973, pp. 373-374.
Murrmann Helmuth
Rathbone Ronald
Schwabe Ulrich
Larkins William D.
Siemens Aktiengesellschaft
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