Patent
1987-10-13
1990-05-08
James, Andrew J.
357 67, 357 69, H01L 2348
Patent
active
049242954
ABSTRACT:
An improved planarization and reliability for low-impendance interconnects in multi-layer wiring of integrated semi-conductor circuits is provided. The circuit comprises at least two metallization levels composed of aluminum or of an aluminum contact, tungsten is employed as a via hole filler and metal silicides are employed as intermediate layers. The metallization pattern contains a nucleation layer preferably composed of titanium/titanium nitride as an under-layer for every metallization level, whereby the electron migration resistance of the aluminum layers is enhanced and a layer preferably composed of molybdenum silicide is used as a cover layer for every metallization level, thereby improving the low-impedance of the metallization. The sandwich-like metallization structure improves the planarity and the thermal stability of the circuit. Since the number of metallization levels is arbitrary, the present invention can be used for VLSI circuits.
REFERENCES:
patent: 3614547 (1971-10-01), May
patent: 4107726 (1978-08-01), Schilling
Gniewek et al., "Titanium Overlay on Metallurgy", IBM Technical Disclosure Bulletin, vol. 13, No. 5, Oct. 1970, p. 1124.
Journal of Vac. Sci. Technology, A2, Apr.-Jun. 1984, pp. 241-242, Kwok et al., "Summary Abstract: Electromigration Studies of Al-Intermetallic Structures".
James Andrew J.
Ngo Ngan Van
Siemens Aktiengesellschaft
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