Integrated sample and hold circuit

Details Integrated sample and hold circuit Integrated sample and hold circuit

1988-07-05

1989-10-10

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 328151, G11C 2702

Patent

active

048734578

ABSTRACT:
A sample and hold circuit made entirely of NPN transistors, capacitors and resistors uses double emitter-follower transistors for gating an input signal onto a charging capacitor. A transistor connected in parallel to the first of the emitter-follower transistors is controlled to conduct blow-by current away from the second emitter-follower transistor in the hold state. A step voltage is applied to the charge capacitor in the hold state to prevent turn on of the emitter-follower transistors. The circuit is configured with complementary components so that a differential output signal eliminating the step voltage is provided.

REFERENCES:
patent: 3286101 (1966-11-01), Simon
patent: 3643110 (1972-02-01), Thompson
patent: 3820033 (1974-06-01), Iwata
patent: 4198541 (1980-04-01), Fukushima
patent: 4542305 (1985-09-01), Blauschild
patent: 4584559 (1986-04-01), Penney
patent: 4636659 (1987-01-01), Sugimoto

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