Integrated RJ-45 magnetics with phantom power provision

Details Integrated RJ-45 magnetics with phantom power provision Integrated RJ-45 magnetics with phantom power provision

2000-07-19

2003-04-01

Sircus, Brian (Department: 2836)

Electrical transmission or interconnection systems

Plural load circuit systems

Transformer connections

C307S412000, C439S490000

Reexamination Certificate

active

06541878

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an apparatus for supplying magnetic transformers and “phantom” power to a multi-pin connector.
BACKGROUND OF THE INVENTION
As processing platforms (including personal computers and network devices) develop greater capability, the industry seeks to reduce the area needed by various components. Such platforms may be represented by a printed circuit board (PCB) and its linked components used for a personal computer, network switch, router, etc. The electrical circuitry for communicating with the platform may be implemented using a transceiver, a transformer (with associated resistors and capacitors) and a connector. Communication may be conducted through a protocol, such as the Institute for Electrical and Electronics Engineers (IEEE) standard 802.3 known as Ethernet™.
The transceiver, also known as “PHY” or &PHgr; (for physical layer), may combine digital adaptive equalizers, phase-lock loops, line drivers, encoders, decoders and other related components. A magnetic transformer may be used to transfer electrical energy from electrically isolated circuits by magnetic fields and fluxes through its windings. The RJ-45 connector, specified under the Telecommunications Industry Association, has eight input pins to the PCB and eight output pins to a jack, with each input pin directly associated with its corresponding output pin. The jack provides a standard receiving port for twisted pair wires connected by a plug to a cable used in 10 BaseT or 100 BaseT Ethernet under IEEE 802.3X.
One method by which required board area on a PHY may be decreased involves component consolidation. The PHY handles the media access control protocols for computer interface communications. The aft region of the PCB, where a RJ-45 cable plug may be inserted into the connector, typically includes magnetic transformers for transferring electronic signals from the PHY to the connector without electrical conduction. The power conduit may also be in proximity to the connector. Typically, the magnetic transformers and power sources are shielded or separated by distance from the connector to minimize noise and electromagnetic interference (EMI).
FIG. 1
shows a schematic for a first conventional eight-pin implementation with discrete magnetics for data-exchange. A connector
10
may be coupled to a PHY
12
through a series of pins by a pair of magnetic transformers
14
. The transformers
14
may be separated from the PHY
12
and the connector
10
by boundaries
16
a
and
16
b
. The PHY
12
may have a pair of receiver ports identified as Rx+ and Rx− along with a complimentary pair of transmitter ports identified as Tx+ and Tx−.
The transformers
14
may be represented by a first 1:1 winding pair
18
a
and a second 1:1 winding pair
18
b
. The windings represent a fine wire wrapped around a core for transmitting power through magnetic fields rather than by electrical conduction. The 1:1 ratio provides voltage out to equal voltage in. Each side of winding pairs may include a center tap. On the PHY or chip input side, the first and second winding pairs
18
a
and
18
b
show first and second taps
20
a
and
20
b
, respectively. On the cable output side, the first and second winding pairs
18
a
and
18
b
show third and fourth taps
20
c
and
20
d
, respectively. A center tap provides the bias voltage from the tapped side of the transformer, with an absolute value typically set to a value above ground as specified by the PHY
12
. For example, if a direct current power source is applied at a center transmitter tap, the transmitter ports Tx+ and Tx− represent differential signals of opposite polarity fluctuating about the bias voltage. The transmitter ports provide the fluctuating voltage difference signal to be transmitted, while the center tap indicates the bias voltage value.
The PHY
12
may include a parallel circuit to the transformers
14
across the receiver ports Rx+ and Rx−. The receiver parallel circuit may include a first pair of 50· resistors
22
a
and
22
b
, with a 1 nf capacitor
24
a
in between and terminating at a fixed potential such as ground
26
. (The capacitor
24
a
may withstand a 50 v surge.) The PHY
12
may also include a parallel circuit to the transformers
14
across the transmitter ports Tx+ and Tx−. The transmitter termination circuit may include a second pair of 50&OHgr; resistors
22
c
and
22
d
, with a 3.3 v voltage source
28
in between and connected to the second center tap
20
b
for the second winding pair
18
b.
On the cable side of the transformer
14
, the fourth center tap
20
d
for the second winding pair
18
b
may be connected to a resonator or termination triplet of 75&OHgr; resistors
30
a
,
30
b
and
30
c
. The first two resistors may be associated with the connector
10
. The third resistor
30
c
may be connected to a 1 nf high potential capacitor
32
that in turn may be connected to ground
26
. (The high potential capacitor
32
may withstand a 2 kv surge.)
The connector
10
may include a series of pins. The RJ-45 connector includes an eight-pin configuration for input coupled to an output port
34
. These may be identified as
36
a
for pin one,
36
b
for pin two,
36
c
for pin three,
36
d
for pin four,
36
e
for pin five,
36
f
for pin six,
36
g
for pin seven and
36
h
for pin eight. The first and second pins
36
a
and
36
b
may be paired to the cable side of the first winding pair
18
a
, thus serving as receiver connections Rx+ and Rx−, respectively. Alternatively, an inductor choke (not shown), used for noise suppression, may serve as a connection between the winding pair
18
a
and the pins
36
a
and
36
b
. The third and sixth pins
36
c
and
36
f
may be paired to the cable side of the second winding pair
18
b
, thus serving as transmitter connections. Tx+ and Tx−, respectively. The fourth and fifth pins
36
d
and
36
e
may be shorted together at line
38
a
and paired to resistor
30
a
connected to the high potential capacitor
32
. The seventh and eighth pins
36
g
and
36
h
may be shorted together at line
38
b
and paired to resistor
30
b.
Thus, pins
36
a
and
36
b
represent a receiver pair and pins
36
c
and
36
f
represent a transmitter pair. In this conventional configuration, only four of the eight pins
36
a
,
36
b
,
36
c
and
36
f
are employed for connections. The other four pins
36
d
,
36
e
,
36
g
and
36
h
remain unused. Connector input and output pins are thereby arranged as follows:
pin no.
connection
1
Rx+
2
Rx−
3
Tx+
4
unused
5
unused
6
Tx−
7
unused
8
unused
The absence of an electrical power supply to the cable side center taps prevents the connector from serving a “telephone” connection or other such power requiring device, in which the power is supplied through the connection. Such a connection may include Ethernet data exchange, voice communication (with internet protocol), a power-consumption device that mimics Ethernet protocol, and measurement sensors.
Such a power source may be transferred by an in-line or “phantom” power source to the transformers at the center taps on the cable side. The term “phantom” refers to using existing wire pairs in Ethernet without additional wire or connector pin overhead. One of the signal pairs on the transformer
18
b
on the cable side may be biased at the direct current (DC) power voltage of the telephone. The other set of signal pairs may be biased at the DC return of the power voltage on the cable side. Since a telephone receiver on the cable side also has transformers for the Ethernet Rx± and Tx± pairs, the DC power from the pairs may supply power to the telephone using magnetic fields and fluxes. For the Tx± and Rx± pairs, the DC component for the bias may be considered “common mode” relative to the differential signals.
FIG. 2A
shows a typical pin layout between the connector and the PCB. The pins or corresponding apertures are arranged as shown in locations
3

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