Integrated register allocation, instruction scheduling, instruct

Details Integrated register allocation, instruction scheduling, instruct Integrated register allocation, instruction scheduling, instruct

1992-11-30

1994-11-22

Eng, David Y.

Boots, shoes, and leggings

3642805, 3642816, 364973, G06F 1200

Patent

active

053676513

ABSTRACT:
An improved register allocator, an improved instruction scheduler, an instruction combiner, and an improved loop unroller is provided to the code generator of a compiler of a computer system. Both the improved instruction scheduler and the improved loop unroller support a "preliminary" and a "final" mode of operation. Upon invocation, the improved register allocator determines and prioritizes regions of the program being compiled. Next, the improved register allocator, in cooperation with the improved instruction scheduler, the instruction combiner, and the improved loop unroller, determines the optimal partitioning for global and local registers for each region. Then, the improved register allocator allocates registers to each region based on the determined number of global registers for the region. After allocating registers for each region, the improved register allocator merges the regions together. The improved loop unroller and the improved instruction scheduler are then invoked successively in "final" mode to unroll the various loops and schedule the instructions being generated.

REFERENCES:
patent: 4782444 (1988-11-01), Munshi
patent: 5261062 (1993-11-01), Sato
D. G. Bradlee, S. J. Eggers, R. R. Henry, Integrating Register Allocation and Instruction scheduling for RISCS, ACM 1991 (ACM 0-89791-380-9/91/0003-0122).

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