Integrated, programmable logic arrangement

Details Integrated, programmable logic arrangement Integrated, programmable logic arrangement

1975-09-29

1976-08-10

Smith, Jerry

Registers

Transfer mechanism

Traveling pawl

307207, 340166R, 3401725, 340173AM, G11C 1500, H03K 1908

Patent

active

039743667

ABSTRACT:
An integrated, programmable logic arrangement includes an AND matrix and an OR matrix which have individual gates. In the AND matrix each input is connected to a control line and via an inverter to another control line for production of a complementary input signal. A selector line and a base line are provided for each gate both in the AND matrix and in the OR matrix and the selector line is connectible to the supply potential. In the AND matrix, in programmed fashion, a switching transistor is provided at the intersection points between a control line and a selector line, or is not so provided, and a switching transistor so arranged at an intersection is connected by its gate terminal to an associated control line, Also, the switching transistor is connected, on the one hand, to an associated selector line of a gate and, on the other hand, to a base line which is connectible to another potential. The difference between the supply potential and the other potential corresponds to the supply voltage. In the OR matrix, in a correspondingly programmed fashion, a switching transistor is provided at an intersection point of a control line and a selector line or is not so provided. A switching transistor so provided is connected by its gate terminal to the associated control line and is connectible, on the one hand, to the selector line of a gate which may be connected to the supply potential and, on the other hand, to a base line which is connectible to ground. In the AND matrix a selector line of a gate is, in each case, connected by way of a pulsed load transistor to the supply potential and the base line of the gate is connectible by way of a pulsed cut-off transistor to the further potential. In the OR matrix, in corresponding fashion, a selector line of a gate is, in each case, connectible via a pulsed load transistor to the supply potential and the base line of the gate is connectible via a pulse cut-off transistor to the further potential. A pulsed flip-flop is arranged, in each case, between an output of the AND matrix and an input of the OR matrix and a pulsed flip-flop is provided, in each case, at an output of an OR matrix.

REFERENCES:
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3816725 (1974-06-01), Greer
patent: 3924243 (1975-12-01), Vermeulen
Kent Andres, "MOS Programmable Logic Arrays," A Texas Instruments Application Report, No. CA-158, Oct. 1970, pp. 1-4.
J. E. Elliott et al., "Array Logic Processing," IBM Technical Disclosure Bulletin, vol. 16, No. 2, July 1973, pp. 586-587.

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